Meng Tong Tan

Analysis and design of power efficient class D amplifier output stages

A Class D amplifier comprises a pulse width modulator and an output stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.

An investigation into the parameters affecting total harmonic distortion in low-voltage low-power Class-D amplifiers

We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the output stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the output stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.

A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity

Class D amplifiers (amps) are conventionally designed as feedforward circuits primarily due to the difficulty of feeding back the digital pulse width modulated output. We analytically investigate the design of Class D amps with feedback and propose a feedback circuit design. We show that the performance of low-power (mWs) low-voltage (1.1-1.4 V) Class D amps embodying our feedback design is significantly improved. The improvements include substantially reduced distortion, improved power efficiency (reduced DC output static bias current), improved gain linearity and lower cost (not requiring post-fabrication trimming), and are achieved with simple hardware. We verify our circuit design proposal by computer simulations and on the basis of measurements on prototype ICs.

Design and analysis of a micropower low-voltage bang-bang control class D amplifier

We describe the design of a novel bang-bang control class D amplifier for low-voltage power-critical applications, including hearing instruments (hearing aids). We analyze the design parameters for the amplifier and determine the relationships between these parameters. The relationships derived herein provide good insight to the design of the amplifier to meet a given specification. We verify our theoretical analyses of some of the design parameters by comparing them against computer simulations. We also show that our bang-bang control class D amplifier features micropower dissipation, low harmonic non-linearities and is suitable for hearing instruments.

A process- and temperature-independent inverter-comparator for pulse width modulation applications

This paper presents a self-tuning inverter-comparator for apulse width modulator (PWM) for Class D amplifiers. The inherentthreshold voltage of the inverter-comparator,VTHC, is independent of process- andtemperature-variations by means of a self-tuning mechanism. Themeasured duty cycle error of the PWM at zero-input is typically0.5%; an error ≤2% is typically specified inpractical realisations. This is achieved without any post-fabricationtrimming or calibration. The PWM is realised by a very simple circuitand can be readily fabricated in a low-cost CMOS process. The PWMprototype ICs met all design specifications and the proposedinverter-comparator is suitable for micropower low-voltageapplications including hearing instruments.

A novel self-error correction pulse width modulator for a class D amplifier for hearing instruments

In this paper, we propose a novel self-error correction pulse width modulator for a class D amplifier for hearing aid applications. The self-error correction mechanisms based on a master-slave architecture is realized by simple digital circuits and can be easily fabricated in a low cost digital CMOS process. The circuit consumes 24.6 /spl mu/A from a 2.5 V supply. Measurements on the prototype IC shows that the error at zero-input 50% duty cycle is less than 2% and the total harmonic distortion is 3.3%.

Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers

The mechanisms for the power supply noise in open-loop single-ended output and H-bridge output PWM class D amplifiers are investigated. Using Fourier series analyses, expressions for power supply rejection ratio (PSRR) and inter-modulation distortion (IMD) are derived. These expressions show that the former OL-CDA topology features a worse PSRR but a better IMD than the latter topology. The derived expressions provide insight to the design of class D amplifiers and the analysis herein can be extended to closed-loop class D amplifiers

A high PSR voltage reference for DC-to-DC converter applications

This paper presents a new 1.2V high power supply rejection (PSR) voltage reference. The proposed design employs a high-PSR pseudo floating voltage source and a differential-to-single-ended R.MOS Capacitor signal-conditioning circuit to achieve high PSR performance metric. The high-PSR pseudo floating voltage source consists of the merged design of two Brokaws reference circuits. The proposed bandgap voltage reference is designed and simulated using CSM 1.8V/3.3V 0.18µm CMOS process technology. At a single 3.3V supply, the simulation results have shown that the reference output voltage can achieve a temperature coefficient of 24.5 ppm/°C over the temperature range from −40°C to 125°C. The PSR is −92.2 dB at dc or very low frequency, −61.8 dB at 1MHz and −42.7 dB at 10MHz, thereby showing that the proposed voltage reference is suitable for DC-to-DC converter applications.

A Class D amplifier output stage with low THD and high PSRR

This paper presents a Class D amplifier output stage with low Total Harmonic Distortion (THD) and high Power Supply Rejection Ratio (PSRR). The Class D output stage reduces the non-linearities and supply noise by means of a second-order negative feedback loop embodying a single stage second-order integrator and a Schmitt trigger comparator. Unlike conventional feedback, the reference input signal of the feedback loop is a digital pulse width modulated signal. The feedback loop compensates for any external errors or non-linearities in the output PWM signal by modulating the pulse width of the output signal. Based on simulation using AMS 0.35µm CMOS process, our proposed closed-loop output stage can achieve a PSRR of .90dB at 1kHz and a THD well below 0.05% up to 10 kHz. This shows that negative feedback can effectively be employed to improve the PSRR and THD performance of a Class D output stage with digital PWM input.

Analysis and two proposed design methodologies for optimizing power efficiency of a class D amplifier output stage

In this paper, we analyze the power dissipation mechanisms and derive the overall power efficiency of a Class D output stage realized using the finger and waffle layouts. We propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency: (i) optimization to a single modulation index point, and (ii) optimization to a range of modulation indices. For the design of an output stage with optimum power efficiency (and small IC area), we recommend the waffle layout realization optimized to a range of modulation indices. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.