Mengshu Huang

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in 0.18 ?m standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is 17.6 ppm/oC, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately 0.03 mm2.

A 4-phase cross-coupled charge pump with charge sharing clock scheme

A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The proposed charge pump is overstress free and compatible for standard CMOS process. Simulation results show a maximum 10% efficiency increase more than that of conventional charge pump without charge sharing.

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

A novel structure of energy efficiency charge recovery logic

A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

A novel charge sharing charge pump for energy harvesting application

A high efficiency charge pump which is suitable for energy harvesting application is proposed. By introducing a pre-charge circuit and a new charge sharing clock scheme, the dynamic power loss caused by parasitic capacitance is reduced by nearly a half. Under an ultralow supply voltage of 0.45V, simulation results show that the efficiency is improved by more than 10%.

Charge sharing clock scheme for high efficiency double charge pump circuit

A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional charge pumps.

A 1.5V four phase switched polarity charge pump

A four phase switched polarity charge pump using 0.13µm triple well CMOS technology is presented. The architecture takes advantage of the threshold voltage cancellation scheme in the conventional four phase Dickson charge pump. With the body control technique, the body effect is eliminated. The charge transfer unit is shared in positive and negative operation, which makes the design more compact. Simulation results show that the proposed 5-stage charge pump can reach +8.22V/−8.05V (ideal: +9V/−9V) with 10% of total capacitance as estimated parastics, and the output indicates good linearity with respect to the increase of stages.

Double charge pump circuit with triple charge sharing clock scheme

A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18µm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8% comparing to 46.8% of a conventional one, and the output ripple voltage is reduced by nearly a half.

Error rate decrease through Hamming weight change for NAND Flash

NAND Flash memory is widely used in recent SoCs. High density NAND Flash requires Error Correcting Code (ECC) mechanism to guarantee data integrity. We propose an efficient ECC model which decrease multi bit errors by considering the Flash memorys characteristic. According to the Flash memory mechanism, 0s error is more likely to happen than 1s error. The proposed error control code counts the number of ‘1’ in a word and inverts all bits to keep the number of 1 is more than that of 0s, which signify a high quantity of Hamming weight. We confirm that the proposed method is not only effective for single error but also dramatically effective for multi bit error.

A nano-power switched-capacitor voltage reference using body effect in MOSFETs for application in subthreshold LSI

Combining switched-capacitor technology with body effect in MOSFETs, a nano-power CMOS voltage reference is implemented in 0.18 μm standard CMOS technology. The low output breaking threshold restriction is produced without using any component subdivision, such that chip area is saved. Measurements show that the output voltage is about 123.3 mV, temperature coefficient is about 17.6 ppm/°C, and line sensitivity is 0.15 %/V. The supply current is less than 90 nA when the supply voltage is 1 V. The area occupation is about 0.03 mm2.