Tsutomu Yoshihara

A Charge Pump Circuit Without Overstress in Low-Voltage CMOS Standard Process

An all PMOS charge pump circuit without over- stress is proposed in low-voltage standard process in this paper. The proposed circuit can reduce the equivalent on-resistance of the charge-transfer transistors and can avoid the body effect due to the two pumping branches architecture. Therefore, its voltage pumping efficiency is much higher than that of the conventional designs. Moreover, the maximum gate-source, gate- drain and drain-source voltages of all transistors in the proposed charge pump circuit do not exceed the power supply voltage Vdd. The proposed charge pump circuit has been realized in a standard CMOS N-Well 0.35 mum technology. The measured results demonstrate that the proposed charge pump circuit has very high voltage pumping efficiency without overstress. Therefore, the proposed circuit is suitable for implementation in low-voltage CMOS standard process.

Clocked CMOS adiabatic logic with low-power dissipation

This paper presents a new low-power adiabatic logic structure called Clocked CMOS Adiabatic Logic (CCAL), which is based on the Clocked CMOS logic. CCAL is powered by two complementary sinusoidal supply clocks. To demonstrate the energy efficiency of CCAL, eight-inverter chain is simulated to show the energy comparison among CCAL, Quasi-Static Energy Recovery Logic (QSERL) and conventional static CMOS with the Rohm 0.18 μm process. The simulation results indicate that CCAL implementation reduces about 40% energy at 200 MHz compared to the static CMOS. And below 100 MHz CCAL eight-inverter chain always has lower dissipation than the QSERL implementation.

A new 7-transistor SRAM cell design with high read stability

The conventional SRAMs, namely four-transistor SRAM (4T) and six-transistor SRAM (6T), suffered from the external noise, because they have direct paths through bit-line(BL) to their storage nodes. This paper proposes seven-transistor (7T) SRAM which has no direct path through BL to the data storage nodes and has higher endurance against external noise. The proposed cell is composed of two separate data access mechanisms; one is for the read operation and another is for the write one. Based upon our SRAM design, data destruction never occurs in the read operation. Simulation result shows that the read Static-Noise-Margin (SNM) of the proposed cell is enhanced by 1.6X and 0.31X with the conventional 4T and 6T SRAM cell respectively. We also manufactured a chip and confirmed its performance.

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in 0.18 ?m standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is 17.6 ppm/oC, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately 0.03 mm2.

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

A charge-recycling circuit and system that reuses the energy between two or more stacked CPUs is proposed in order to double the life of a battery. In this architecture, CPUs are divided into upper and lower load groups, and electrical charges are shared among the stacked CPUs and a tank capacitor. Charges are temporarily stored in the tank capacitor and are then reused. To control divided loads, a high-speed and energy-efficient regulator is needed. Internal circuit voltage variation between the upper and lower modules is determined by seven low-drop-out (LDO) regulators, a voltage-boosting capacitor circuit, and the tank capacitor. As a result, stable voltage can be supplied to each CPU, even if the upper and lower loads are different or a battery is being used. The LDOs improve the margin of collection in the tank capacitor or task schedule operation, and power efficiency is raised even further. The circuit can be implemented on silicon without a large external control circuit and inductor such as a switching regulator. This circuit was applied to an in-vehicle lock-step system because the upper and lower loads and tasks are the same. Additionally, by using the proposed task scheduling to maximize efficiency, this circuit can be applied not only to lock-step systems but also to general systems. Test chips were fabricated using 90-nm standard CMOS technology. Although the maximum power efficiency of a conventional circuit with a simple LDO is 44.4%, efficiency of the proposed charge-recycling circuit turned out to be as high as 87.1% with the test chips.

A 4-phase cross-coupled charge pump with charge sharing clock scheme

A 4-phase cross-coupled charge pump with charge sharing clock scheme is proposed in this paper. Four phase clock is utilized to prevent the reverse leakage current. A charge sharing clock control circuit is constructed, and the consumption in charging or discharging the bottom plate parasitic capacitance of the boost capacitors is reduced by half. The proposed charge pump is overstress free and compatible for standard CMOS process. Simulation results show a maximum 10% efficiency increase more than that of conventional charge pump without charge sharing.

A 1pJ/cycle Processing Engine in LDPC application with charge recovery logic

This paper presents a Processing Engine (PE) which is used in Low Density Parity Codec (LDPC) application with a novel charge-recovery logic called pseudo-NMOS boost logic (pNBL), to achieve high-speed and low power dissipation. pNBL is a high-overdriven, low area consuming charge recovery logic, which belongs to boost logic family. Proposed Processing Engine is used in LDPC circuit to reduce power dissipation and increase the processing speed. To demonstrate the performance of proposed PE, a test chip is designed and fabricated with 0.18μm CMOS technology. Simulation results indicate that proposed PE with pNBL dissipates only 1pJ/cycle when working at the frequency of 403MHz, which is only 36% of PE with conventional static CMOS gates. The measurement results shows that the test chip can work as high as 609MHz with the energy dissipation of 2.1pJ/cycle.

A novel structure of energy efficiency charge recovery logic

A novel charge-recovery logic structure called Pulse Boost Logic (PBL) is proposed in this paper. PBL is a high-speed low-energy-dissipation charge-recovery logic with dual-rail evaluation tree structure. It is driven by 2-phase non-overlap clock, and requires no DC power supply. To demonstrate the performance of PBL structure, 4-bit counters designed with both PBL gates and conventional static CMOS. Post-layout simulation is applied to compare energy dissipation performance between PBL and conventional static CMOS in a frequency range of 500MHz to 1GHz. The simulation result indicates that PBL dissipates only 15% energy per cycle at 1GHz, and for sequential circuits such as counter, PBL is less area consuming than static CMOS.

A Fast Lock Phase-Locked Loop Using a Continuous-Time Phase Frequency Detector

A continuous-time phase frequency detector (PFD) based on the conventional tri-state PFD is proposed for fast lock charge pump phase-locked loops (CPPLLs) in this paper. The locking time of the PLL can be substantially reduced with the proposed continuous-time scheme. During the period that the best tracing and acquisition properties are required, the bandwidth of the PLL can be increased to decrease the locking time with the proposed continuous-time PFD. Afterwards, the bandwidth of the PLL is recovered to the original value to minimize output jitter due to external noise. Any conventional tri-state PFDs can be improved with the proposed continuous-time architecture. The proposed architecture is realized in a standard CMOS 0.35 mum technology. The simulation results demonstrate that the proposed continuous-time PFD is effective to get more speedy locking time.

A novel charge sharing charge pump for energy harvesting application

A high efficiency charge pump which is suitable for energy harvesting application is proposed. By introducing a pre-charge circuit and a new charge sharing clock scheme, the dynamic power loss caused by parasitic capacitance is reduced by nearly a half. Under an ultralow supply voltage of 0.45V, simulation results show that the efficiency is improved by more than 10%.