Mervyn Armstrong

Low Temperature Bonding of PECVD Silicon Dioxide Layers

The bonding of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide layers, deposited at 300oC, to thermal silicon dioxide layers is described. The PECVD oxide requires pre-bond annealing and CMP for void free bonding. Post bond annealing for bond strengthening must be performed at a lower temperature than the pre-bond annealing step. Bond strengths of 1J/m2 have been achieved after bond annealing at 400oC. This bonding method can be used in layer/circuit transfer and has been demonstrated with the transfer of a 2µm SOI layer from one substrate to another.

Micro-Raman and Spreading Resistance Analysis on Beveled Implanted Germanium for Layer Transfer Applications

D Micro-Raman and Spreading Resistance Analysis on Beveled Implanted Germanium for Layer Transfer Applications Paul Rainey,* Joanna Wasyluk, Tatiana Perova, Richard Hurley, Neil Mitchell, David McNeill, Harold Gamble,* and Mervyn Armstrong School of Electrical Engineering and Computer Science, Northern Ireland Semiconductor Research Center, The Queen’s University of Belfast, Belfast, BT9 5AH, Northern Ireland, United Kingdom Department of Electronic and Electrical Engineering, University of Dublin, Trinity College, Dublin 2, Ireland

Germanium on sapphire

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge, GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 μm and has a very low loss tangent (α) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing.

Back Gate Effects in N-Channel Monocrystalline Silicon Devices-on-Glass and their Suppression by Boron Ion Implantation

Initial N-channel self aligned polycrystalline silicon gate transistors fabricated on 1.5μm -2μm single crystal Silicon-O-Glass(SOG) layers exhibited poor transfer characteristics. Measured threshold voltages and On/Off current ratios were in the order of -8V and 10 respectively. This is due to the presence of fixed charge at the bond interface introducing back gate effects which degrade and distort device performance. These back gate effects were suppressed by implantation of boron into the silicon substrate prior to oxidation and bonding, with energy 40keV and dose 7.4×10 12 cm −2 . This resulted in an improvement in device performance with a threshold voltage of-0.54V. On/Off current ratio increased to 1840 and field effect mobility increased from 274cm 2 /Vs to 357cm 2 Vs

Multiple self-aligned iron nanowires by a dual selective chemical vapor deposition process

have also been reported. In this paper, we demonstrate a self-aligning technique that allows the fabrication of organized parallel iron nanowires on a planar edge silicon and silicon dioxide surface. The desired number of parallel wires is formed by repeating a series of polysilicon deposition and oxidation steps. The planarized surface for nanowire formation was defined by CMP and the iron wires were produced using a novel double selective CVD process. In this work, tungsten hexafluoride WF6 and iron pentacarbonyl FeCO5 were the respective tungsten and iron precursors. The dimensions and spacing of the iron wires were determined by the thickness of the thermal oxide and deposited polysilicon layer respectively, and not by any lithographic tool. Very accurate alignment was achieved with this method. The multiple iron nanowires proposed in this paper have possible applications in magnetic field measurement and calibration devices in pressure sensing where the resistivity of long thin iron resistors changes under stress. Possibly the most interesting application for this technology is in the formation of tunable diffraction gratings. Under the influence of an electromagnetic field, the properties of the iron will change, which may allow a switching mode in the grating. Figure 1 shows substrate preparation and the deposition of multiple parallel iron nanowires. 4 m deep trenches were etched into the silicon substrates in an inductively coupled plasma ICP system with SF6 and C4F8 plasmas Fig. 1a. The trenches were then refilled

Multiphysics Simulation of Electromagnetic Shielding and Thermal Stressing within Ceramic and Silicon Multilayer Packages for RF Applications

A multiphysics finite element method (FEM) based software, COMSOLtrade has been used to simulate coupled electromagnetic shielding and thermal stress issues for system-in-package (SiP) modules. The ceramic and silicon carriers under study have embedded shielding ground planes. Power HEMT RF devices in GaAs technologies are embedded on and within the carrier causing local thermal hotspots. Thermal cooling is performed using thermal vias. The electromagnetic interaction of thermal vias with the embedded ground plane is studied for hole clearance and via size

LPCVD of tungsten by selective deposition on silicon

Tungsten has been deposited in a low pressure chemical vapor deposition (LPCVD) system by silicon reduction of WF6. Hydrogen passivation of the silicon was found essential to inhibit native oxide formation on the silicon. A self-limiting W thickness of 100 nm was achieved at a deposition temperature of 440 °C. A typical layer sheet resistance of 2 Ω/□ was obtained. Layers deposited at higher temperature yielded greater thickness, but showed the inclusion of higher resistivity β phase W.WSi2 also observed, indicating solid phase reaction between the silicon and the deposited W. A reduced self-limiting thickness of W was observed when heavily doped single-crystal substrates were employed. This reduction in thickness was also observed when polycrystalline samples were employed.

Shallow junction and contact realization by diffusion of heavily doped polycrystalline-germanium for Ge devices

In conclusion, a unique method to achieve high quality shallow n+/p junction by out-diffusion of phosphorus from poly-Ge has been demonstrated. The technology and key issues of poly-Ge deposition by LPCVD is presented. Results shown from diode I-V characteristics indicate feasibility of poly-Ge used for junction and contact realization.

Ultra-shallow emitter formation for germanium bipolar transistor by diffusion from polycrystalline germanium

Germanium, with a higher electron mobility than in silicon and with the highest hole mobility, has promise for high performance CMOS circuits. However, for many analogue circuits, bipolar transistors are preferred as they generate less noise than MOS devices. To exploit the high carrier mobility in Ge for RF applications it is therefore necessary to investigate the fabrication of bipolar transistors in germanium. The adoption of modern technology for Ge BJTs is a challenging technical task. The authors have previously described novel Ge BJT technology for successful device manufacture.[1] Typical output characteristics of a BJT manufactured with an implanted emitter are shown in Fig.1. RF BJTs require tight control of emitter junction depth and base width. It is therefore essential to develop polycrystalline emitter structures to achieve this. In this paper, a polycrystalline Ge process has been developed and applied for the first time in n+ emitter formation and contact realization. This has been investigated by manufacture of diode structures by an innovative method, which employs phosphorus out-diffusion a from doped poly-germanium layer. SIMS has been employed to profile the phosphorus diffusions undertaken at several temperatures and drive-in times. The Athena simulation programme has been adapted to model this process in Ge and phosphorus diffusivity parameters have been extracted.

Circular geometry transistors fabricated on germanium-on-alumina bonded substrates

Germanium(Ge) has attractive properties such as high carrier mobility, compatibility with high-K dielectrics, and lattice matched for GaAs growth. Germanium on insulator (GOI) (1) offers the advantages of germanium and combines them with those of silicon on insulator (SOI). Bonding to substrates which are thermally matched to Ge eases process temperature constraints and can have additional benefits depending on the substrate used. Transistors have previously been reported on a germanium on sapphire wafer bonded platform (2). Fine grain alumina offers a cheaper alternative to sapphire while still retaining advantages such as low substrate losses and better crosstalk suppression. In this work Circular Geometry MOS transistors fabricated and tested on germanium bonded to a fine grain alumina substrate (superstrate 997) are presented. The Ge on Alumina substrate was realised by bonding a polysilicon coated and subsequently planarised alumina substrate to a Umicore 2.7-2.9 ohmcm n-Ge substrate(3). After subsequent bond strength annealing at 150 C the Ge was thinned by precision in-house grinding and diamond particulate polishing leaving a thick 100μm Ge on Alumina layer. The ground and polished substrate is shown in figure 1. Circular geometry transistors were fabricated using a low temperature self aligned W gate fabrication process. The maximum temperature seen by the transistors was 450 C. The transistors having a W/L of 9 also employed a 20nm APCVD silicon dioxide layer as the gate dielectric. As a direct comparison identical transistors where fabricated on bulk Ge substrates with the same resistivity as the bonded structure. Figure 2 shows the resultant output characteristics obtained from both the bulk Ge device (2(a)) and the Ge on Alumina device (2(b)). As can be seen the bulk Ge showed better transistor characteristics exhibiting an effective mobility of 480 cm/Vs compared to 150cm/Vs. The Ge on Alumina substrate also shows significant series resistance. The decline in device performance was thought to be due to the poor surface roughness of the Ge on Al layer after polishing. It was found that by the addition of NaOCL into the polish process an improvement in the surface roughness of germanium was achieved from 2.5nm to 0.8nm.. Subsequently transistors fabricated on the improved reworked Ge layer produced improved characteristics comparable to those obtained in bulk Ge. Characteristics shown in figure 3 exhibit an effective mobility of 414 cm/Vs Low temperature investigation of the transistor operation on the Ge on Al devices was carried out over a range of temperatures from room temperature to 173 K on transistors having a W/L of 9. A MDC model 441 cryogenic probe station in combination with Agilent B1500 parameter analyser was employed for low temperature measurement. Device characteristics were seen to improve with an increase in effective mobility (μeff) and decrease in Sub threshold slope (S) observed with decreasing temperature. The improvement in transistor effective mobility is shown in figure 4. Table 1 offers a summary of the change in device characteristics with decreasing temperature.