David McNeill

Silicon-on-insulator substrates with buried tungsten silicide layer

Abstract Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.

Comparison of Si1−yCy films produced by solid-phase epitaxy and rapid thermal chemical vapour deposition

Abstract Thin Si 1− y C y films with a range of carbon contents have been prepared by both solid-phase epitaxy (SPE) and rapid thermal chemical vapour deposition (RTCVD) techniques. For SPE growth, layers with carbon levels of up to 1.6 at.% exhibit strong substitutional incorporation. For RTCVD growth, substitutional carbon incorporation is difficult to achieve at a growth temperature of 800 °C, but has been achieved in layers estimated to contain 2 at.% carbon at a growth temperature of 700 °C. These results indicate that strain-compensated growth of Si 1− x − y Ge x C y with a wide range of composition should be possible in the present RTCVD system at temperatures of approximately 700 °C.

Geometric linewidth and the impact of thermal processing on the stress regimes induced by electroless copper metallization for Si integrated circuit interconnect technology

Mechanical strains and stresses are a major concern in the development of copper-based on-chip metallization. Synchrotron x-ray topography (SXRT), micro-Raman spectroscopy, finite element modeling (FEM), and atomic force microscopy (AFM) have been used to examine the strain fields imposed by electroless Cu metallization on the underlying Si. As expected, we have observed enhanced strain regions close to the metal line edges. These strain fields tend to zero at annealing temperatures approaching 200 ° C, and thereafter the magnitudes of the strain fields at 300 ° C and 400 ° C are much higher, implying a return to a higher strain regime. Although the strain transition point is slightly different from the SXRT result, the FEM results confirm the existence of a zero-strain transition point as a function of thermal anneal. We have also examined the generated stress in Si as a function of Cu linewidth L. We have found that the stress sXX due to the electroless copper metallization is empirically related to the Cu linewidth in terms of an exponential distribution. For Cu linewidths less than 20 mm, the stress magnitudes increased with decreasing Cu linewidth due to the thermal stress in the absence of self-annealing, whereas the stress decreased with increasing linewidths in the range of 60‐ 100 mm due to a relief of the thermal stress possibly via the self-annealing effect. This self-annealing phenomenon was observed using AFM. It is observed that the stresses in the Si shifted to a compressive state after annealing at 400 ° C.

Low temperature fabrication and characterization of nickel germanide Schottky source/drain contacts for implant-less germanium p-channel metal-oxide-semiconductor field-effect transistors

In this work, nickel germanide Schottky contacts have been fabricated on n-type germanium (n-Ge) with an optimum barrier height of 0.63 eV. For rapid thermal annealing (RTA) temperatures above 300  °C, all phases of nickel and germanium convert to nickel mono-germanide (NiGe). However, higher RTA temperatures are also found to cause agglomeration of the NiGe phase and higher leakage current. So, the optimum temperature for Schottky-based source/drain contact formation on n-Ge is ∼300 °C, where the nickel mono-germanide phase is formed but without phase agglomeration.

Fermi level de-pinning of aluminium contacts to n-type germanium using thin atomic layer deposited layers

Fermi-level pinning of aluminium on n-type germanium (n-Ge) was reduced by insertion of a thin interfacial dielectric by atomic layer deposition. The barrier height for aluminium contacts on n-Ge was reduced from 0.7 eV to a value of 0.28 eV for a thin Al2O3 interfacial layer (∼2.8 nm). For diodes with an Al2O3 interfacial layer, the contact resistance started to increase for layer thicknesses above 2.8 nm. For diodes with a HfO2 interfacial layer, the barrier height was also reduced but the contact resistance increased dramatically for layer thicknesses above 1.5 nm.

Soft x-ray photoemission study of the thermal stability of the Al2O3/Ge (100) interface as a function of surface preparation

The high temperature thermal stability of ultra-thin atomic layer deposited Al2O3 on sulphur passivated and hydrofluoric acid (HF) treated germanium surfaces was studied using soft x-ray photoemission spectroscopy. The interface sulphur component was stable up to 500 °C vacuum annealing. The interfacial oxides were completely removed at 600 °C for the sulphur passivated sample, whereas HF treated sample showed traces of residual oxides at the interface. However, this annealing treatment does not show any significant change in Al2O3 stoichiometry. The dielectric-semiconductor band offsets were estimated using photoemission spectroscopy measurements.

Investigation of germanium implanted with hydrogen for layer transfer applications

The technology for thin Ge layer transfer by hydrogen ion-cut process is characterised in this work. Experiments were carried out to determine suitable hydrogen ion implantation doses in germanium for the low temperature ion cut process by examining the formation of blisters on implanted samples. Raman and Spreading Resistance Profiling (SRP) have been used to analyse defects in germanium caused by hydrogen implants. Bevelling has been used to facilitate probing beyond the laser penetration depth. Results of Raman mapping along the projection area reveal that after post implant annealing at 400 °C, some crystal damage remains, while at 600 °C, the crystal damage has been repaired. SRP shows that some amount of hydrogen acceptor states (~1Î1016 acceptors/cm2) remain after 600 °C. These are thought to be vacancy-related point defect clusters.

Low Temperature Bonding of PECVD Silicon Dioxide Layers

The bonding of plasma enhanced chemical vapor deposition (PECVD) silicon dioxide layers, deposited at 300oC, to thermal silicon dioxide layers is described. The PECVD oxide requires pre-bond annealing and CMP for void free bonding. Post bond annealing for bond strengthening must be performed at a lower temperature than the pre-bond annealing step. Bond strengths of 1J/m2 have been achieved after bond annealing at 400oC. This bonding method can be used in layer/circuit transfer and has been demonstrated with the transfer of a 2µm SOI layer from one substrate to another.

Micro-Raman and Spreading Resistance Analysis on Beveled Implanted Germanium for Layer Transfer Applications

D Micro-Raman and Spreading Resistance Analysis on Beveled Implanted Germanium for Layer Transfer Applications Paul Rainey,* Joanna Wasyluk, Tatiana Perova, Richard Hurley, Neil Mitchell, David McNeill, Harold Gamble,* and Mervyn Armstrong School of Electrical Engineering and Computer Science, Northern Ireland Semiconductor Research Center, The Queen’s University of Belfast, Belfast, BT9 5AH, Northern Ireland, United Kingdom Department of Electronic and Electrical Engineering, University of Dublin, Trinity College, Dublin 2, Ireland

Optimisation and scaling of interfacial GeO 2 layers for high-k gate stacks on germanium and extraction of dielectric constant of GeO 2

Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon. In this paper, GeO 2 has been investigated as an interfacial layer for high-k gate stacks. Thermally grown GeO 2 layers have been prepared at 550 °C to minimize GeO volatilization. GeO 2 growth has been performed in both pure O 2 ambient and O 2 diluted with N 2 . GeO 2 thickness has been scaled down to 3.15 nm. MOS capacitors have been fabricated using different GeO 2 thicknesses with a standard high-K dielectric on top. Electrical properties and thermal stability have been tested up to at least 350°C. The k value of GeO 2 was calculated as 4.5. Interface state densities (D it ) of less than 1012 cm−2 eV1 have been extracted for all devices using the conductance method.