Suli Suder

Improved Thermal Performance of SOI Using a Compound Buried Layer

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.

A high performance 36V complementary bipolar technology on low thermal resistance compound buried layer SOI substrates

In this paper a new high voltage, high performance, high packing density, silicon complementary bipolar technology on novel low thermal resistance compound buried layer (CBL) SOI is reported. NPN and Vertical PNP devices have been fabricated with matched DC and AC characteristics, cut-off frequencies of 3 GHz and breakdowns greater than 36 Volts. The thermal resistance and substrate capacitance of the fabricated devices confirms the superior performance of the CBL SOI substrates.

Circular geometry mos transistor analysis of SOI substrates for high energy physics particle detectors

SOI substrates are important for the fabrication of monolithic active pixel high energy physics particle detectors. In this work, self-aligned circular geometry MOS transistor test structures were fabricated on ion split, bonded SOI substrates to evaluate the interface between the high resistivity handle silicon and the SOI buried oxide. Pre- and post- proton irradiation transistor measurements are presented, showing an increased SOI buried oxide trapped charge of only 3.45times1011 cm-2 for a dose of 2.7 Mrad.