Mesut Atasoyu

Design of current-mode class 1 frequency-agile filter employing CDTAs

In this study, in order to demonstrate the versatility of the active building block so-called current differencing transconductance amplifier (CDTA), a current-mode (CM) frequency-agile filter (FAF) application circuit is designed. The derived 2nd-order class 1 CM FAF employs three CDTAs, two capacitors and a single resistor. A layout is designed for CDTA and post-layout simulations are performed using CADENCE Spectre tool with TSMC 0.18 μm level-49 CMOS technology process and BSIM3v3 parameters. The simulation results confirm theoretical findings.

Spin-torque memristor based offset cancellation technique for sense amplifiers

In this study, we propose an offset cancellation technique with the spin-torque memristors where are unpredictable threshold voltage changes of transistors that results in the input referred random offset (IRRO) of amplifiers. Motivated by this fact, this study focuses on the IRRO cancellation in sense amplifiers with the aid of the spin-torque memristor technology. The spin-torque memristors in series perform less resistance and process variations from parallel connection. The resistance value of the spin-torque memristor was regarded as frozen when the current flow over the spin-torque memristor is lower than its critical switching current value. In fact, the proposed structure employs a non-destructive sensing scheme in order to achieve a relatively large sense margin by reducing the IRRO. Our main idea is to reduce or eliminate the IRRO exploiting the spin-torque memristors for providing the current matching on the input transistors of the voltage comparator. In particular, the overwrite problem of the spin-torque memristor was solved by setting the critical switching current of the spin-torque memristor to be greater than a current value corresponding to maximum the IRRO value. We evaluated the IRRO cancellation technique on the proposed comparator or sense amplifier using 45nm predictive CMOS technology. Although sense amplifiers are targeted in this study, our technique can be applied to any analog amplifier suffering from the IRRO.

Low power frequency agile filter application for different GPS protocols

In this paper, second and fourth order frequency agile filter applications realized with second generation current controlled current conveyor is presented. Encrypted communication, cognitive radio and software defined radio structures use the frequency agile filter structure. These systems background need the reconfigurable frequency receveirs, oscillators or etc. The designed frequency agile filter structure is also applicable to the global positioning systems(GPS, GLONASS, Beidou, GNSS and Galileo) to be processed on a single discrete filter. The performance of the reconfigurable filter is verified in Cadence environment. AMS 0.18 μm process paremeters are used for the simulations.

A tunable immitance simulator with a voltage differential current conveyor

In this paper, an electronically tunable immitance circuit is proposed. The presented circuit can be configured as a tunable grounded inductor or capacitor multiplier. The proposed circuit employs a single active element called Voltage Differential Current Conveyor, a single resistor and a single capacitor. The presented circuit does not require element matching constraints. It is linearly tunable over four decades of frequency using bias current control. Simulation results are included to verify theory.

Design of a power output unit for HF transmitters

In this paper, complete power output unit for an high-frequency (3-30MHz) transmitter system is presented. The system consists of a 4:1 power combiner block, a power control unit which is vital for the effective operation of the system and four commercially available power amplifiers. In order to achieve high-performance, we have focused on the design of power combiners and power control unit. To this end, modeling and analysis of power combiners are reconsidered and an efficient power combiner realization based on double-sided parallel-striplines is obtained. Using the proposed power combiners and the designed power control unit, the overall 1000W high-frequency output stage is built and its performance is verified via measurements results.

Wideband hybrid power combiner using double-sided-parallel-strip lines

A new design of a hybrid power combiner using double-sided parallel-striplines is proposed for wideband and high power applications. The circuit is used to realize a 4:1 power combiner. The use of double-sided parallel-strip lines adds flexibility to the design, since different characteristic impedances can readily be realized by simply adjusting the offset between parallel lines, without having to change the width of the lines. Moreover, a new approach using ferrite cores in order to improve low frequency performance of the power combiner is successfully applied. The proposed power combiner is studied analytically; its performance is verified via detailed HFSS simulations and measurements results.

Frequency agile filter structure improved by MOS-only technique

In this paper, a new frequency agile filter structure for analog signal processing is proposed by using of MOS only technique. In contrast to the conventional analog building blocks, the filter is designed with only MOS transistors. The parasitic capacitances of the MOS transistor are used instead of the classical capacitors. The operating frequency range is improved and the power consumption is decreased. The simulations have been performed in Cadence environment using 0.18μm TSMC parameters.

Reconfigurable filter structure designed for different positioning systems

Second and fourth order reconfigurable filter structure implemented with second generation current controlled current conveyor is presented in this paper. Reconfigurable filter structure is widely used on the basis of the encrypted communication, cognitive radio and software defined radio systems. The designed filter is applied to the global positioning systems (GPS, GLONASS, Beidou, GNSS and Galileo) to be processed on a single discrete filter. The layout and the post - layout simulations is verified for the designed filter. AMS0.18μm process parameters and CADENCE environment are used for the simulations.