Mesut Meterelliyoz

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technology is presented. The designs of a 0.092 μm2 bitcell for high density applications and a 0.108 μm2 bitcell for improved performance at low supply voltage are introduced. Transient voltage collapse and wordline under-drive peripheral assist circuits improve low-voltage operating margins and address fin quantization. Co-optimization of tri-gate transistors and circuits allow up to 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm2.

Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM

A novel transient voltage collapse (TVC) technique is presented to enable low-voltage operation in SRAM. By dynamically switching off the PMOS during write operations with a collapsed supply voltage below the data retention voltage, a minimum operating voltage (Vccmin) of 0.6V is demonstrated in a 32nm 12-Mb low-power (LP) SRAM. Data retention failure of unselected cells is mitigated by controlling the duration of voltage collapse. Circuit-process co-optimization is critical to ensure robust circuit design margin of TVC technique.

A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design

With transistor feature size scaling and higher integration density, power density has become a major problem. High power density results in elevated on chip temperature, which has significant impacts on power consumption and circuit reliability. In this work, we have presented a temperature adaptive design technique using a low overhead CMOS temperature sensor. We have shown that, by online monitoring of temperature, circuit power consumption can be adjusted adaptively so as to stabilize the chip temperature and achieve a robust design

Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits

In this work, we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28nm FinFET based circuits as they are more prone to thermal runaway compared to bulk-MOSFETs. We generate thermal models for logic cells to self-consistently determine the temperature map of a circuit block. Our proposed condition for thermal runaway shows the design trade off between the primary input (PI) activity of a circuit block, sub-threshold leakage at the room temperature and the thermal resistance of the package. We show that in FinFET circuits, thermal runaway can occur at the ITRS specified sub-threshold leakage (150nA/mum, high-performance) for a nominal PI activity of 0.5 and typical package thermal resistance

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology

CMOS technology scaling continues to drive higher levels of integration in VLSI design, which adds more compute engines on a die. To meet the overall performance-scaling needs, high-speed and high-bandwidth memory is becoming increasingly important. Conventional VLSI systems often rely on on-die SRAMs to address the performance gap between CPU and main memory, DRAM. However, with the rapid growth in capacity needs for high-performance memory, SRAM is not always sufficient to meet the demands of bandwidth-intense applications. Embedded DRAM (eDRAM) has been explored as an alternative to satisfy the high-performance and density needs in memory [1-3]. In this paper, a high-performance eDRAM based on a 22nm tri-gate CMOS technology is introduced. This eDRAM technology enables the integration of an eDRAM cell into the logic technology platform [4]. The design features a well-balanced configuration to achieve both optimal array efficiency and bandwidth. By leveraging the high-performance and low-voltage tri-gate transistor at 22nm generation, the eDRAM achieves a wide range in operating voltage, from 1.1V down to 0.7V, which is essential for low-power logic applications.

A leakage control system for thermal stability during burn-in test

Increase in leakage current with technology scaling has been a major problem for IC technology. This problem becomes more crucial during burn-in test where stressed voltage and temperature are applied. Due to presence of a positive feedback between major components of leakage and temperature in CMOS circuits, excessive leakage may lead to thermal runaway and yield loss during burn-in test. This paper describes a novel integrated leakage control system to ensure thermal stability during burn-in test for a wide range of ambient temperatures and process variations

Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor

We propose a novel ultralow-power, high-sensitivity, bias-free sub-threshold process variation sensor for monitoring the random variations in the threshold voltage. The proposed sensor characterizes the threshold voltage mismatch between closely spaced, supposedly identical transistors using the exponential current-voltage relationship of sub-threshold operation. The sensitivity of the proposed sensor is 2.3× better than the previous sensor reported in the literature which utilizes above-threshold operation. To further improve the sensitivity of the proposed sensor, an amplifier stage working in the sub-threshold region is designed. This enables 4× additional increase in sensitivity. A test-chip containing an array of 128 PMOS and 128 NMOS devices has been fabricated in 65-nm bulk CMOS process technology. A total of 28 dies across the wafer have been fully characterized and the random threshold voltage variations are reported here.

Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits

In this paper, we propose a methodology to solve leakage power self-consistently with temperature to predict thermal runaway. We target 28-nm-technology-node FinFET-based circuits as they are more prone to thermal runaway because of self-heating and less efficient heat dissipation compared to bulk metal-oxide-semiconductor field-effect transistors. We have generated thermal models for logic cells-inverter, NAND, and NOR-to self-consistently determine the temperature map of a circuit block. Our cell-level thermal models account for lateral heat flow (contribution of neighboring cells) along with vertical heat dissipation to the heat sink. We predict positive feedback between subthreshold leakage and temperature for all the cells in a given floor plan. Our proposed condition for thermal runaway shows the design tradeoff between the primary input (PI) activity of a circuit block, subthreshold leakage at the room temperature, and thermal resistance of the package. We show that, in FinFET circuits, thermal runaway can occur at the International Technology Roadmap for Semiconductors-specified subthreshold leakage (of 150 for high performance) for a nominal PI activity of 0.5 and typical package thermal resistance. In addition, we show that the maximum temperature rise in an integrated circuit is limited by package limitations.

Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology

With technology scaling, elevated temperatures caused by increased power density create a critical bottleneck modulating the circuit operation. With the advent of FinFET technologies, cooling of a circuit is becoming a bigger challenge because of the thick buried oxide inhibiting the heat flow to the heat sink and confined ultra-thin channel increasing the thermal resistivity. In this work, we propose compact thermal models to predict the temperature rise in FinFET structures. We develop cell-level compact thermal models for standard INV, NAND and NOR gates accounting for the heat transfer across the six faces of a cell. Temperature maps of benchmark circuits exhibit close correspondence with dynamic power maps because of confined regions of heat generation separated by low thermal conductivity material. It is illustrated that temperature-aware timing analysis is imperative, because of high inter-cell temperature gradient. Accurate prediction of temperature in the early phase of design cycle gives valuable estimation of power/performance/reliability of a circuit block and guides in the design of more robust circuits

Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

A high performance eDRAM technology has been developed on a high-performance and low-power 22nm tri-gate CMOS SoC technology. By applying noise reduction circuit techniques and extensive device and design co-optimization on eDRAM bitcell and critical circuits, over 100μs retention time at 95°C has been achieved for a Gbit eDRAM with robust manufacturing yield.