Yih Wang

Erratic fluctuations of sram cache vmin at the 90nm process technology node

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage. This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional. Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause. The erratic Vmin phenomenon can be eliminated for 90 nm SRAMs by process optimization. However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array. A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active V MIN -enhancing assist circuitry

Future product applications demand increasing performance with reduced power consumption, which motivates the pursuit of high-performance at reduced operating voltages. Random and systematic device variations pose significant challenges to SRAM VMIN and low-voltage performance as technology scaling follows Moores law to the 22nm node. A high-performance, voltage-scalable 162Mb SRAM array is developed in a 22nm tri-gate bulk technology featuring 3rd-generation high-k metal-gate transistors and 5th-generation strained silicon. Tri-gate technology reduces short-channel effects (SCE) and improves subthreshold slope to provide 37% improved device performance at 0.7V. Continuous device width sizing in planar technology is replaced by combining parallel silicon fins to multiply drive current. Process-circuit co-optimization of transient voltage collapse write assist (TVC-WA) and wordline underdrive read assist (WLUD-RA) features address process variation and fin quantization at 22nm and enable a 175mV reduction in the supply voltage required for 2GHz SRAM operation. Figure 13.1.1 shows an SEM top-down view of a 0.092μm2 high-density 6T SRAM bitcell (HDC) and a 0.108μm2 low-voltage 6T SRAM cell (LVC) after gate and diffusion processing. Computational OPC/RET techniques extend the capabilities of 193nm immersion lithography to allow a 1.85× increase in array density relative to 32nm designs [1].

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

SRAM bitcell design margin continues to shrink due to random and systematic process variation in scaled technologies and conventional SRAM faces a challenge in realizing the power and density benefits of technology scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. This paper introduces an adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die. The ADWLUD sensor enables 130 mV reduction in SRAM Vccmin while increasing frequency yield by 9% over conventional SRAM without WLUD. The sensor area overhead is limited to 0.02% and power overhead is 2% for a 3.4 Mb SRAM array.

A 1.1 GHz 12

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.

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A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed

A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

CMOS technology has followed Moores law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role in determining the scaling of SRAM operating voltage (VCC), frequency and leakage power. We develop a high-performance voltage-scalable SRAM design in 32nm logic CMOS featuring 2nd-generation high-κ metal-gate transistors and 4th-generation strained silicon [1]. With the continued transistor performance enhancement and extensive process-circuit co-optimization, the 32nm SRAM design is able to achieve 2× improvement in density and 15% faster access speed when compared to the 45nm design [2] at the same voltage. The design supports a broad range of operating voltages to enable dynamic voltage scaling in todays high-performance and low-power applications. The design also features an integrated power management scheme with close-loop array leakage control, floating bitline and wordline driver sleep, resulting in 58% reduction of SRAM leakage consumption.

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

A 162 Mb voltage-scalable SRAM array design in 22 nm CMOS tri-gate logic technology is presented. The designs of a 0.092 μm2 bitcell for high density applications and a 0.108 μm2 bitcell for improved performance at low supply voltage are introduced. Transient voltage collapse and wordline under-drive peripheral assist circuits improve low-voltage operating margins and address fin quantization. Co-optimization of tri-gate transistors and circuits allow up to 70% improvement in frequency at low voltages and 85% improvement in density from a scaled 32 nm design. The low-voltage array design demonstrates 4.6 GHz operation at 1.0 V and 3.4 GHz operation at 0.8 V while achieving array densities up to 6.7 Mb/mm2.

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm Lgate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

A novel transient voltage collapse (TVC) technique is presented to enable low-voltage operation in SRAM. By dynamically switching off the PMOS during write operations with a collapsed supply voltage below the data retention voltage, a minimum operating voltage (Vccmin) of 0.6V is demonstrated in a 32nm 12-Mb low-power (LP) SRAM. Data retention failure of unselected cells is mitigated by controlling the duration of voltage collapse. Circuit-process co-optimization is critical to ensure robust circuit design margin of TVC technique.

A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.