Fatih Hamzaoglu

Circuit-level techniques to control gate leakage for sub-100 nm CMOS

Although still negligible for state-of-the-art CMOS, gate leakage will become significant in the future for sub-100nm technologies, due to the scaling of oxide thickness. We propose several circuit techniques to control gate leakage based on the fact that PMOS transistors with SiO2 gate oxide have an order of magnitude smaller gate leakage than NMOS transistors in the same technology. First, we compare n-type domino with p-type domino circuits in terms of performance, leakage and switching power, and explore the different tradeoffs between performance and power. Second, we compare n-type with p-type gating for MTCMOS to control the leakage during sleep. The proposed circuits are simulated for a predictive 70nm CMOS technology with 10Å gate oxide thickness and 1.2V supply voltage.

Analysis of dual-V/sub T/ SRAM cells with full-swing single-ended bit line sensing for on-chip cache

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

Split-path skewed (SPS) CMOS buffer for high performance and low power applications

Splitting a regular multistage CMOS buffer into two separate paths, and then skewing each path in opposite directions to achieve faster delay leads to a new, high-speed, split-path skewed (SPS) CMOS buffer. The two skewed paths are statically merged in the final stage such that the short-circuit current is eliminated without tri-stating the output. The proposed circuit is simulated for various skew values in a 0.18 /spl mu/m CMOS technology for a 1.8 V supply voltage. The SPICE simulation results validate the fast operation of the proposed buffer and show that the energy delay product is always reduced and, for a skew value of four, the delay with respect to a regular tapered buffer design is reduced by 28% to 34%.

Non-Manhattan maze routing

The availability of multiple metal layers in modern IC processes raises the possibility of using non-Manhattan routing on some of the layers in order to reduce the average interconnect length, and thus improve performance and routability. In this paper, we present novel algorithms for both Manhattan and non-Manhattan multi-layer maze routing. The algorithms in principle can be extended to an arbitrary number of layers, but the paper focuses on four-layer routing, two in horizontal and two in vertical directions for Manhattan, and one layer each in horizontal, vertical, 45-degree and 135-degree directions for non-Manhattan routing. The non-Manhattan algorithms show an improvement of up to 12.2% in average wire length compared to Manhattan routing for two general MCNC benchmarks.