Michael A. Shore

Method and apparatus for storage of test results within an integrated circuit

Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs

Device and method for repairing a memory array by storing each bit in multiple memory cells in the array

Reducing digit equilibrate current during self-refresh mode

Structure and a method for storing information in a semiconductor device

DRAMs having on-chip row copy circuits for use in testing and video imaging and method for operating same

Detection of row-to-row shorts and other row decode defects in memory devices

Apparatus and method for increasing test flexibility of a memory device

Hardware implemented row copy enable mode for DRAMS to create repetitive backgrounds for video images or DRAM testing

Combination column redundancy system for a memory array