Michael D. Deal

High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates

Ge on insulator (GOI) is desired to obtain metal-oxide-semiconductor transistors with high performance and low leakage current. We have developed a method to make GOI based on liquid-phase epitaxial (LPE) growth on Si substrates and a defect necking technique in which defects are confined to a very short distance. Self-aligned microcrucibles were used to hold the Ge liquid. High-quality single-crystal (100) as well as (111) oriented GOI structures were obtained with a process compatible with Si-based fabrication. No dislocations or stacking faults were found in the LPE Ge films on insulator. The orientation of the Ge crystals was controlled by the seeding Si substrate. This method opens up the possibility of integrating Ge device structures in a baseline Si integrated circuit process.

Nature of germanium nanowire heteroepitaxy on silicon substrates

Systematic studies of the heteroepitaxial growth of germanium nanowires on silicon substrates were performed. These studies included the effect of sample preparation, substrate orientation, preanneal, growth temperature, and germane partial pressure on the growth of epitaxial germanium nanowires. Scanning electron microscopy and transmission electron microscopy were used to analyze the resulting nanowire growth. Germanium nanowires grew predominantly along the ⟨111⟩ crystallographic direction, with a minority of wires growing along the ⟨110⟩ direction, irrespective of the underlying silicon substrate orientation [silicon (111), (110), and (100)]. Decreasing the partial pressure of germane increased the number of ⟨111⟩ nanowires normal to the silicon (111) surface, compared to the other three available ⟨111⟩ directions. The growth rate of nanowires increased with the partial pressure of germane and to a lesser degree with temperature. The nucleation density of nanowire growth and the degree of epitaxy both...

Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/ and HfO/sub 2/

In this letter, we investigate a method to adjust the gate work function of an MOS structure by stacking two metals with different work functions. This method can provide work function tunability of approximately 1 eV as the bottom metal layer thickness is increased from 0 to about 10 nm. This behavior is demonstrated with different metal combinations on both SiO/sub 2/ and HfO/sub 2/ gate dielectrics. We use capacitance-voltage (C-V) characteristics to investigate the effect of different annealing conditions and different metal/metal bilayer couples on the work function. By comparing the as-deposited and annealed films, and by comparing with metals that are relatively inert with each other, we deduce that the work function tuning behavior likely involves metal/metal interdiffusion.

Microstructure of thermal hillocks on blanket Al thin films

The microstructure of thermal hillocks on blanket Al thin films has been studied for the first time by several techniques, including sectioning and imaging in a focused ion beam system. It is found that the new material in the hillock area lifts the original film up and in some cases penetrates it. The micrographs also reveal the grain structures and give valuable insight into the mechanisms of hillock growth.

Rapid Melt Growth of Germanium Crystals with Self-Aligned Microcrucibles on Si Substrates

A rapid melt growth method was developed to produce Ge crystals including Ge pillars, nanowires, and Ge-on-insulator. Amorphous Ge was deposited and patterned, then crystallized by melting and solidifying using Si substrates for seeding. Self-aligned SiO 2 microcrucibles were used to contain the Ge liquid during the crystallization anneal. The misfit defects were terminated within small regions around the seeding windows by a necking mechanism. Crystallization calculations showed that very high epitaxial growth velocity can be achieved when the temperature of Ge liquid is lower than but close to its melting point, while the random unseeded nucleation rate is very low in the same temperature range. High-quality Ge nanowires and Ge-on-insulator structures are produced with a simple and robust process. The rapid melt growth technique works very well with a variety of film thickness, including that of nanometer ultrathin structures. The surface smoothness obtained by Ge deposition is retained during crystallization and the film thickness is also controlled by deposition.

Ion implantation into gallium arsenide

Secondary‐ion‐mass‐spectrometry studies of the implantation profiles of 20‐ to 400‐keV Si, Se, and Be ions into GaAs are reported. The measured profiles are fit with Pearson‐IV distributions whose moments are fit to functions of the ion energy to obtain simple, widely applicable analytical formulas. Also, profiles are measured for varying wafer tilt and rotation angles to the ion beam, and for varying dislocation densities and doses. For implantation through dielectric caps, the profiles in the GaAs can be simulated using shifted, bare‐wafer Pearson‐IV distributions for Be, or mixtures of shifted Pearson‐IV and Gaussians for Si and Se. Also, knock‐on distributions of Si and O atoms resulting from implanting through SiO2 caps were measured.

Study of the effect of grain boundary migration on hillock formation in Al thin films

We have studied the effect of grain boundary migration on hillock formation in unpassivated Al thin films during thermal cycling. Hillocking occurs more frequently in Al films that experience grain growth during thermal cycling than in films with stabilized grain structures. The hillocking frequency is at least four times greater in the films that experience grain growth, as judged by the number of hillocks observed per initial grain boundary triple junction. This latter measure takes account of the smaller initial grain size in the film that experiences grain growth and shows that grain boundary migration itself must enhance the hillocking frequency.

Modeling uphill diffusion of Mg implants in GaAs using suprem‐iv

Transient, uphill diffusion of implanted Mg in GaAs during a 900 °C anneal is simulated using suprem‐iv. The diffusion is believed to occur via the substitutional‐interstitial‐diffusion (SID) mechanism, with excess interstitials and vacancies produced by the implantation process causing this abnormal diffusion behavior. The SID mechanism is shown to be equivalent, in terms of the governing equations, to the interstitial‐dopant pair diffusion model used in suprem‐iv. This allows one to use suprem‐iv, a silicon process simulator that includes dopant–point‐defect interactions, to model uphill diffusion once the appropriate diffusivity and defect parameters are included. The profiles of excess interstitials and vacancies produced by the implantation process are obtained from Boltzmann transport equation calculations. The transient uphill diffusion phenomenon can be well simulated using the diffusion model in suprem‐iv, with the dopant diffusing from the region of excess interstitials toward the surface and the region of excess vacancies. Once the defect concentrations return to their steady‐state levels, either by diffusion, recombination, or capture by sinks, the normal concentration‐dependent diffusion into the substrate occurs.

Physical model of the impact of metal grain work function variability on emerging dual metal gate MOSFETs and its implication for SRAM reliability

A new model of work function variability (WFV) based on grain orientation differences of the polycrystalline metal gate is reported. Our model predicts that at the 22 nm technology node, among the three device variability sources: random dopant fluctuation (RDF), line edge roughness (LER) and WFV, WFV will cross over RDF and becomes the dominating factor. The SRAM circuit analysis shows that write/read failures are underestimated by 9 orders of magnitude by the area weighted averaged work function model.

Diffusion of implanted beryllium in n‐ and p‐type GaAs

The diffusion of ion‐implanted Be in GaAs is studied by comparing the diffusion of implanted Be in undoped GaAs and in GaAs uniformly doped with Zn or Si. The Si‐doped sample exhibits much less Be diffusion compared to the undoped case, while the Zn‐doped sample shows much more Be diffusion. The diffusion in the doped substrate cases can be simulated with a constant Be diffusivity, as opposed to a concentration‐dependent diffusivity in the undoped case. The results are consistent with the substitutional‐interstitial diffusion mechanism, which predicts a diffusivity that is dependent on the net hole concentration.