James D. Plummer

Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces

Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particulary as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface mobilities. It is the purpose of this paper to present an extensive set experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. Empirical equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO 2 interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.

Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's

We present a scaling theory for fully-depleted, cylindrical MOSFETs. This theory was derived from the cylindrical form of Poissons equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFETs was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.

Activation and diffusion studies of ion-implanted p and n dopants in germanium

We have demonstrated symmetrically high levels of electrical activation of both p- and n-type dopants in germanium. Rapid thermal annealing of various commonly implanted dopant species were performed in the temperature range of 600–850 °C in germanium substrates. Diffusion studies were also carried out by using different anneal times and temperatures. T-SUPREM™ simulations were used to fit the experimental profiles and to extract the diffusion coefficient of various dopants.

High-quality single-crystal Ge on insulator by liquid-phase epitaxy on Si substrates

Ge on insulator (GOI) is desired to obtain metal-oxide-semiconductor transistors with high performance and low leakage current. We have developed a method to make GOI based on liquid-phase epitaxial (LPE) growth on Si substrates and a defect necking technique in which defects are confined to a very short distance. Self-aligned microcrucibles were used to hold the Ge liquid. High-quality single-crystal (100) as well as (111) oriented GOI structures were obtained with a process compatible with Si-based fabrication. No dislocations or stacking faults were found in the LPE Ge films on insulator. The orientation of the Ge crystals was controlled by the seeding Si substrate. This method opens up the possibility of integrating Ge device structures in a baseline Si integrated circuit process.

VLSI Process modeling—SUPREM III

Over the past several years, the process-simulation tool SUPREM II has proven useful in the design and optimization of both bipolar and MOS technologies. This paper describes a new and significantly more capable version of the program--SUPREM III--which incorporates process models suitable for VLSI device design. This new version of the program is now generally available and should provide a powerful new tool in VLSI design. For the first time, the program models multilayer structures (up to five material layers). It also incorporates substantially upgraded diffusion, oxidation, ion implantation, and other process models. These models incorporate, where possible, recent thinking about underlying physical mechanisms. The program remains a one-dimensional simulator; extensions to two dimensions are discussed. This paper concentrates on the process models and their underlying physics; implementation issues are addressed elsewhere.

Chemistry of Si‐SiO2 interface trap annealing

The kinetics and chemistry of Si‐SiO2 interface trap annealing are examined in detail. Measurements of interface trap density Dit as a function of anneal time were performed with several process variables as parameters: oxide thickness, anneal ambient, temperature, bulk carrier type, metallization damage, and orientation. Experiments were carried out using rapid thermal processing and capacitance‐voltage measurements of aluminum gate metal‐oxide‐semiconductor capacitors. Anneal temperature and crystal orientation have the strongest effect on the kinetics. 〈100〉 interfaces can be described by a power‐law temporal variation; 〈111〉 kinetics are slightly more complicated. In both cases the experimentally observed anneal behavior is in conflict with the commonly used second‐order surface recombination model. We propose a two‐reaction model involving atomic hydrogen dimerization and hydrogen/interface trap reactions. This model sucessfully predicts anneal kinetics over a temperature range of 170–500 °C, represe...

Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors

Power MOS transistors have recently begun to rival bipolar devices in power-handling capability. This new capability has arisen primarily through the use of double-diffusion techniques to achieve short active channels and the incorporation of a lightly doped drift region between the channel and the drain contact, which largely supports the applied voltage. Many different structures have been proposed to implement these new devices. This paper considers three of the most common-LDMOS, VDMOS, and VMOS. Structural differences which result in on-resistance and transconductance differences between the devices are described. Quantitative models, suitable for device design, are developed for the on-resistance of each type of structure. These models are developed directly from the physical structure (geometry and doping profiles) so that they are useful in optimizing a particular device structure or in quantitatively comparing structures for a particular application.

Impact ionization MOS (I-MOS)-Part I: device and circuit simulations

One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and I/sub ON/>1 mA//spl mu/m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.

Gettering of gold in silicon: A tool for understanding the properties of silicon interstitials

The movement of gold in silicon is controlled by the reaction of gold with silicon interstitials, not by the intrinsic diffusion coefficient of gold. This fact is used to understand the role silicon interstitials play during gettering in silicon. An analysis of gold profiles after gettering reveals that high concentration phosphorus diffusion, argon‐ion implantation, and mechanical damage of a silicon surface all act as sources of silicon interstitials. This finding is experimentally confirmed by studying the effect of an argon implanted surface layer on the diffusion of both phosphorus and antimony buried layers; only the phosphorus layer shows an enhancement, which is consistent with the injection of silicon interstitials. Studying the enhancement of the phosphorus diffusion versus temperature reveals that the phosphorus‐interstitial pair has a migration energy of 1.3 eV. Under the assumption of local equilibrium between silicon interstitials and phosphorus atoms, estimates of the diffusion coefficient ...

Fractional contributions of microscopic diffusion mechanisms for common dopants and self-diffusion in silicon

An identical set of thermal oxidation and nitridation experiments has been performed for four common dopants and self-diffusion in Si. Selectively perturbing the equilibrium point-defect concentrations by these surface reactions is a powerful tool for identifying the relative importance of the various atomic-scale diffusion mechanisms. We obtain bounds on the fractional contributions of the self-interstitial, vacancy, and concerted exchange mechanisms for arsenic, boron, phosphorus, antimony, and self-diffusion in Si at temperatures of 1100 and 1000 °C. These bounds are found by simultaneously solving a system of equations making only very conservative assumptions. The validity of common approximations found in previous work and their effects on the results are also analyzed in detail. We find that B and P diffuse by a self-interstitial mechanism, whereas Sb diffusion is almost exclusively vacancy mediated. As and self-diffusion, on the other hand, exhibit evidence for a dual vacancy-interstitial mechanis...