Michaël F. X. B. van Swaaij

Deriving ASIC architectures for the hough transform

Abstract In this paper two novel ASIC systolic array architectures for the Hough transform will be derived from a single behavioural description. The main result presented in this paper is that, by using methodical nonlinear transformations, non-uniform (and non-affine) recurrence equations can be mapped efficiently onto regular array architectures with realistic area and I/O constraints.

Memory and Data-Path Mapping for Image and Video Applications

In this chapter, we will present a high-level synthesis methodology that is particularly suited for irregular high-throughput subsystems realized on an application-specific architecture. This Cathedral-3 methodology is targeted to real-time signal processing applications with a low potential for time multiplexing, as occurring, for example, in image and video applications. The most crucial steps in this methodology are supported by appropriate synthesis techniques embedded in prototype tools. The emphasis lies on high-level synthesis supporting the dominant design cost factors, i.e., an area-efficient memory organization and a customized data-path configuration, both within the stringent throughput requirements. The power of the approach will be illustrated with realistic demonstrators.

Affine transformations for multi-dimensional signal processing on ASIC regular arrays

The problems involved with high-level synthesis of ASIC regular arrays for multi-dimensional signal processing applications will be outlined. The goal is to map nonuniform recurrence equations on regular arrays with realistic constraints on area, throughput and I/O bandwidth. Algorithms for multi-dimensional signal processing often involve a large number of indices. In this paper, novel techniques are presented that are needed to map these multi-index algorithms onto regular arrays with limited dimension.<<ETX>>

Modeling Data Flow and Control Flow for DSP System Synthesis

A data flow and control flow model is presented for use in high level synthesis of efficient time multiplexed architectures targeted towards real-time DSP systems. The model is an extension to the polyhedral models used in array synthesis techniques. The model features a mathematical description of dependencies between individual operations and signal instances of multi-dimensional signals for algorithms that can be described by Conditional Affine Recurrence Equations. It allows for a generalization of high level control flow transformations and their steering by efficacious optimization methods. The inherent amenity of this type of model for these tasks is motivated by examples. Important tasks in high level synthesis that can exploit this model are memory management for time multiplexed architectures and non-linear transformations for array architectures, but also other tasks may benefit. The former task will be described in more detail in this paper.

Nonlinear transformations for high level regular array ASIC synthesis

In this paper a new and efficient method is presented for optimizing the mapping ofnonuniform recurrence equations on regular array architectures. The method is based on applyingnonlinear transformations on theindices of the recurrence equations by reindexing groups of operations based on a chosen group communication scheme. The main result of this paper is that the presented method provides a means to map real life high throughput algorithms onto ASIC regular array architectures under real constraints.

Regular Array Synthesis for Image and Video Applications

This chapter presents some results obtained at IMEC and IRISA in the field of regular array synthesis for real-time image and video applications. A fully tuned design methodology is presented that leads to an efficient array architecture for our target domain, starting from a true behavioral description. The power of this methodology is demonstrated on a complex real-life application: a full video motion estimation design. The necessary array synthesis techniques are also introduced, with emphasis on the non-conventional ones.

Novel regular-array ASIC architecture for 2-D ROS sorting

In this paper a novel regular array architecture for the 2-D running order statistics sort problem will be presented. The architecture combines a high throughput in terms of sorted windows with low hardware costs and low I/O bandwidth. It will be shown that the throughput-hardware cost ratio is substantially better than that of previously published architectures for this sorting problem under the same I/O constraints. This has been achieved by a careful design of the sorting algorithm that is tuned to match as tightly as possible the needs of real-life applications requiring this type of sorting. This design illustrates that designing algorithms with both precise applications and an architectural style in mind can greatly reduce the cost of VLSI Application Specific Integrated Circuit (ASIC) implementation. In this way it enhances the feasibility of a VLSI implementation of an algorithm.