Hugo De Man

Compensation of IQ imbalance and phase noise in OFDM systems

Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.

Instruction set definition and instruction selection for ASIPs

Application Specific Instruction set Processors (ASIPs) are field or mask programmable processors of which the architecture and instruction set are optimised to a specific application domain. ASIPs offer a high degree of flexibility and are therefore increasingly being used in competitive markets like telecommunications. However, adequate CAD techniques for the design and programming of ASIPs are missing hitherto. An interactive approach for the definition of optimised microinstruction sets of ASIPs is presented. A second issue is a method for instruction selection when generating code for a predefined ASIP. A combined instruction set and data-path model is generated, onto which the application is mapped.<<ETX>>

Background memory area estimation for multidimensional signal processing systems

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity. >

A generalized state assignment theory for transformations on signal transition graphs

In this article, we propose a global assignment theory forencoding state graph transformations. A constraint satisfaction framework is proposed that can guaranteenecessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is free of critical races. Performing transformations at the state graph level has the advantage that the requirements imposed on the initial STG are very weak. Unlike previous methods, the initial STG need not be a live, safe, nor a free choice net. The only requirement is that the corresponding initial state graph is finite, connected, and has a consistent state assignment. Hence, a very broad range of signal transition graphs can be synthesized. The transformations achievable using the proposed framework correspond to very complex transformations on signal transition graphs. Even transformations that convert a free choice net into a correct non-free choice net and a 1-safe net into a correct 2-safe net are feasible. Addition of transitions that do not follow the Petri net firing rule is also possible. Even though our method can search a large solution space, we will show that it is possible to solve the problem in an exact way in acceptable CPU times in many practical cases.

Space-time block coding for single-carrier block transmission DS-CDMA downlink

The combination of space-time block coding (STBC) and direct-sequence code-division multiple access (DS-CDMA) has the potential to increase the performance of multiple users in a cellular network. However, if not carefully designed, the resulting transmission scheme suffers from increased multiuser interference (MUI), which dramatically deteriorates the performance. To tackle this MUI problem in the downlink, we combine two specific DS-CDMA and STBC techniques, namely single-carrier block transmission (SCBT) DS-CDMA and time-reversal STBC. The resulting transmission scheme allows for deterministic maximum-likelihood (ML) user separation through low-complexity code-matched filtering, as well as deterministic ML transmit stream separation through linear processing. Moreover, it can achieve maximum diversity gains of N/sub T/N/sub R/(L+1) for every user in the system, irrespective of the system load, where N/sub T/ is the number of transmit antennas, N/sub R/ the number of receive antennas, and L the order of the underlying multipath channels. In addition, it turns out that a low-complexity linear receiver based on frequency-domain equalization comes close to extracting the full diversity in reduced, as well as full load settings. In this perspective, we also develop two (recursive) least squares methods for direct equalizer design. Simulation results demonstrate the outstanding performance of the proposed transceiver compared to competing alternatives.

System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach

A battery powered multimedia communication device requires a very energy efficient implementation. The required efficiency can only be acquired by careful optimization at all levels of the design. System-level power optimizations have a dramatic impact on the overall power budget. We have proposed a system-level step-wise methodology to reduce the power in hardware realizations of data-dominated applications, which is partly supported with our ATOMIUM environment. In this paper, we extend the methodology to the realization of embedded software on processor cores. Starting from a high level algorithm description (e.g., in C), a set of optimizations gradually refine the code and the corresponding memory organization of the array data types. These array data types represent a fully detailed optimized data storage and transfer organization. Instead of creating the physical memories, a mapping can be done either on a general memory architecture, including a cache, or on a custom memory architecture. First, typical optimizations addressed by our methodology are applied on a didactical example. The effectiveness of this methodology is then demonstrated by the optimization of two complex applications in an embedded processor context: a MPEG2 and a H.263 video decoder. The impact of the power optimizations on the typical power consumption is demonstrated by simulating the optimized decoders with real video streams.

A graph based processor model for retargetable code generation

Embedded processors in electronic systems typically are tuned to a few applications. Development of processor specific compilers is prohibitively expensive and as a result such compilers, if existing, yield code of an unacceptable quality. To improve this code quality, we developed a retargetable and optimising code generator. It uses a graph based processor model that captures the connectivity the parallelism and all architectural peculiarities of an embedded processor In this paper; the processor model is presented and we formally define the code generation task, including code selection, register allocation and scheduling, in terms of this model.

An Efficient Microcode-Compiler for Custom DSP-Processors

In this paper, a microcode compiler for custom DSP-processors is presented. This tool is part of the CATHEDRAL II silicon compiler. Two optimization problems in the microcode compilation process are highlighted: microprogram scheduling and memory allocation. Algorithms to solve them, partly based on heuristics, are presented. Our compiler successfully handles repetitive programs, and is able to decide on hardware binding. In most practical examples, optimal solutions are found. Whenever possible, indications of the complexity are given.

Efficient system exploration and synthesis of applications with dynamic data storage and intensive data transfer

Matisse is a design flow intended for developing embedded systems characterized by tight interaction between control and data-flow behavior, intensive data storage and transfer, dynamic creation of data, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip HW/SW implementation. Matisse supports stepwise system-level exploration and refinement, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for HW synthesis, SW compilation, and HW/SW interprocessor communication synthesis. Application of Matisse on telecom protocol processing systems shows significant improvements in area usage and power consumption.

In-place memory management of algebraic algorithms on application specific ICs

High level memory management is an important step during the automatic synthesis of application specific micro coded processors aimed at multi-dimensional signal processing in real-time. For given throughput and I/O flow requirements, the objective is to derive the optimal background memory organization where the cost due to storage size and address requirements are minimized. In this paper, a contribution will be proposed to this complex problem. A strategy will be presented to detect the possibility forin-place storage and to deduce thememory requirements for the implementation of numerical matrix type of algorithms on a single ASIC chip.