Michael Feil

The challenge of ultra thin chip assembly

Because of their low height, the low assembly topography and their mechanical flexibility, ultra thin chips (about 20 /spl mu/m) offer a wide field of possible applications. During the last years, the Fraunhofer-Institute for Reliability and Microintegration has successfully investigated in production, handling and assembly processes for such thin ICs. The chip handling and assembly processes had to be adopted to the very thin material, beginning with the development of special dicing by thinning process. A new pick and place process using thermal releasable tapes has been developed. For the chip assembly and contacting various methods depending on the application are available. This includes face up or face down variations. The complete process chain from wafer processing up to the assembled ultra thin IC together with some application examples are discussed in this paper.

Innovative packaging concepts for ultra thin integrated circuits

The increasing demand on miniaturized and flat packaging technologies is driven by the trend towards small and portable electronic systems. Due to the requirements of modern Ball Grid Arrays, Smart Cards or Chip Size Packages thickness of integrated circuits has been reduced considerably compared with original wafer thickness. Driven by this evolution, the Fraunhofer Institute for Reliability and Microintegration has advanced its wafer thinning technology down to a residual silicon thickness of 20 /spl mu/m and below. Because of low height, low topography of assembled chips and mechanical flexibility, these chips are ideal for integration in thin and bendable systems or vertically stacked systems. The advantages of thin ICs open a large field of new and interesting applications in microelectronics. However wafer thinning has its impact on subsequent assembly process. Dicing, handling, mounting and interconnection processes of thin ICs has to fulfil particular requirements, but also offers new and innovative solutions. These are investigated and discussed in this paper.

Simultaneous fabrication of dielectric and electric joints by wafer bonding

Wafer bonding is a key technology for the fabrication of micro mechanical systems which consist of two or more stacked silicon parts. Among the different bonding methods anodic bonding with an intermediate layer of Pyrex glass offers several advantages concerning the process flexibility and the stability of the bond. To use this technology the sputter deposition process of Pyrex glass was optimized and the anodic bonding process was characterized. A process for a capacitive pressure sensor was designed which included bond frames made out of sputtered glass. The electrical contact from both electrodes to contact pads was realized by lateral and vertical feedthroughs. The latter were obtained by an Au-Au thermocompression bond which was simultaneously fabricated with the anodic bond.

Studies of fine pitch patterning by reel-to-reel processes for flexible electronic systems

Cost effective and high quality processes are needed for further development of flexible electronic systems. Applications of these structures are e. g. in the field of high density interconnection foils or polymer electronics. In this paper a lithography process for patterning copper on flexible foils using reel-to-reel methods is presented. The process allows the fabrication of well defined copper structures with typical feature sizes from 15 to 40 /spl mu/m using either etching or electroplating technology. Properties of the dry film photoresist used in the process as well as details of the technology are described. Influences of photolithography and etching on dimensional accuracy and resolution are given and some consequences on design rules are shown.

Thin Chips for Flexible and 3D-Integrated Electronic Systems

Thin chip work at the IZM aims to develop an integrated approach from the Thinning of product wafers over related chip separation and handling techniques to the application of useful assembling processes to bring the thin chip safely into the product and to allow a reliable operation. After an introduction to thin chip applications the chapter focuses on the development of thinning processes and explains the different thinning techniques applied. In a strong correlation the handling and wafer preparation is described in detail. In a further part the correlated assembly processes are presented in a relation to possible product or application scenarios. Thinning, Dicing, Handling and Assembly Processes for Thin Chips are developed at the Fraunhofer IZM-M together in an Optimized and Integrated Approach. The choice of a thinning process in many cases defines already the boundary conditions of the separation handling or assembly process of a product. Therefore having the product in view none of the processes can be developed in an isolated manner. The chapter finishes with a short outlook and the introduction of reel to reel processing of systems with thin chips and manufacturing of low-cost thin chip products in the IZM reel to reel application center.

Fast flip chip assembly for reel-to-reel manufacturing

For low-cost applications like smart labels, a mounting technology, which allows high throughput is necessary. Therefore, such products are fabricated reel-to-reel on flexible substrates. With this technology, cheap substrate materials can be used and substrate handling is reduced to a minimum, but to achieve fast production cycles it is important to establish rapid and efficient mounting technologies. Flip chip assembly using anisotropic conductive adhesive (ACA) offers an inexpensive method interconnecting many contacts simultaneously, but mounting speed is limited by the fact that a defined pressure has to be maintained during curing. For chips with only a few contacts, alternative methods which allow higher throughput are investigated.

A New Method of Flip Chip Assembly Using a Light Silver Filled Glue

Automated and cost-efficient manufacturing processes are of paramount importance for low-cost mass products. One for a bottle neck of the manufacturing transponder is the present chip assembly. ICs are assembled by flip chip adhesive technology using anisotropic or non-conductive adhesives. Simultaneous, both pressure and temperature are required, meaning a high process engineering complexity for mass products. An adhesive, lightly filled with Ag, is used in the proposed new development. Pressure is required but momentarily during placing the chip. For curing only temperature is used. Contact resistance in the range of mOhm and insulation resistance between neighboring bond pads of >20 MOhm were realised and proved by test chips

Investigation of the adhesion mechanism of NiCr layers on Al/sub 2/O/sub 3/ and AlN substrates

Sputtered NiCr layers on Al/sub 2/O/sub 3/ and AlN substrates show a very high adhesive strength in pull tests. An effort was made to investigate, with analytical procedures, the adhesion mechanism responsible for this. For the characterization of the surfaces and layers, element analyses were carried out with X-ray photoelectron spectroscopy and Auger electron spectroscopy. High-resolution transmission electron microscopy (HRTEM) studies were performed on a qualitative basis in order to obtain lattice fringes and lattice images of the thin overlayer and the substrate in near-interface regions. The results obtained lead to the conclusion that, with both ceramics, the good adhesion is due to the chemical bonding between Cr, Al, and O.<<ETX>>

Ultra-Flat "Mounted" Electronics

The paper proposes a method to place encapsulated devices with a size of typically 100 mum micro capsules of this size can be fabricated in batch processes, and they can be dispensed or printed by coarse screen printing techniques. The electric properties of a desired element are roughly defined by the printing pattern, not by the single micro capsule. This means a lot of capsules form a single device. In order to provide an oriented deposition, as necessary in case of polarization dependent deposition, a magnetic alignment is proposed