Karlheinz Bock

Influence of gate length on ESD-performance for deep sub micron CMOS technology

The ESD performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 /spl mu/m CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD thresholds, leading to an optimum performance for longer gate length devices attributed to the trade-off between power dissipation and melt volume of the parasitic bipolar device.

ESD issues in compound semiconductor high frequency devices and circuits

The need of (electrostatic discharge) ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis to ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.

Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 /spl mu/m CMOS technology

An electrostatic discharge (ESD) evaluation of a silicided 0.25 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology is carried out by HEM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Pulsed stress reliability investigations of schottky diodes and HBTS

Experimental results from stressing Schottky diodes and HBTs employing TLP (Transmission Line Pulses) with 100ns duration time and ESD pulses following the Human Body Model are compared. Based on optical and electrical characterisation the same failure mechanisms seem to occur indicating the strong degree of relationship between these two methods. Device failures are explained by thermally activated interface and bulk reactions, field enhanced material transport and hot charge carrier effects.

Influence of gate length on ESD-performance for deep submicron CMOS technology

The ESD performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 /spl mu/m CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD thresholds, leading to an optimum performance for longer gate length devices attributed to the trade-off between power dissipation and melt volume of the parasitic bipolar device.

Characterisation of reliability of compound semiconductor devices using electrical pulses

Transmission line pulses (TLP) with 0-60V amplitude and 100ns pulse width have been applied for accelerated lifetime tests of GaAs devices. 1/f noise, RF noise and I/V measurements are applicable for the characterisation of the reliability of these devices. Different failure mechanisms can be identified by applying square pulses of varying amplitude and different polarity on a variety of samples. Correlation between anomalies in 1/f noise, RF noise and I/V characteristics has been determined. Using this novel method, the determination of failure threshold levels for current density, electric field and charge carrier temperature is possible and critical spots in device design can be ascertained.

Investigation into socketed CDM (SDM) tester parasitics

The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly affects the SDM failure threshold voltage levels and may lead to miscorrelation and nonreproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides 10 to 20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.

ESD issues in compound semiconductor high-frequency devices and circuits

The need of ESD protection for high frequency devices and circuits is underlined by reviewing the compound semiconductor material properties with emphasis on ESD stress and by collecting their ESD failure thresholds. Basic requirements for possible ESD protection structures in the microwave frequency regime are discussed and possible ESD protection devices and circuit concepts are proposed.

A compact model for the grounded-gate nMOS transistor behaviour under CDM ESD stress

Abstract The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching of both, drain and source, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. Furthermore, a fast analytical method to determine CDM ESD lumped tester parasitics from measured pulse characteristics is presented. The triggering of the grounded gate nMOS transistor under CDM is studied in detail for different gate lengths. The optimal gate length for CDM protection in advanced submicron technologies is discussed.

ESD protection methodology for deep-sub-micron CMOS

Electrostatic discharge is considered to be a serious treat of integrated CMOS circuits since the feature size reached about 1.5-1.0μm. Since then the scaling of CMOS technologies led to an increase of their ESD susceptibility based on geometrical, physical and technological limitations. The paper describes the change in methodology in order to assure a reasonably high target value of ESD protection with newly to be developed deep sub-micron feature size technologies. The backward adaptive conservative methodology is step by step replaced by a methodology considering the ESD issue already during process development and involving more predictive ESD-TCAD into the development cycle. It is concluded that the scaling based limitations might grow to a significant problem in the near future requiring significant effort to assure a reasonable ESD protection level for CMOS technologies, in particular if the high-frequency properties of such technologies should not be affected.