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Dive into the research topics where Michael G. Butler is active.

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Featured researches published by Michael G. Butler.


international symposium on microarchitecture | 2011

Bulldozer: An Approach to Multithreaded Compute Performance

Michael G. Butler; Leslie Barnes; Debjit Das Sarma; Bob Gelinas

AMD bulldozer module represents a new direction in microarchitecture and includes a number of firsts for AMD, including AMD multithreaded X86 processor, implementation of a shared level 2 cache, and X86 processor to incorporate floating-point multiply-accumulate (FMAC). This article discusses the module multithreading architecture, power-efficient micro architecture, and subblocks, including the various microarchitectural latencies, bandwidths, and structure sizes.


ieee hot chips symposium | 2010

Bulldozer a new approach to mult ithreaded compute performance

Michael G. Butler

This article consists of a collection of slides from the authors conference presentation on AMDs Bulldozer, the companuys approach to multithreaded computer architecture. Some of the specific topics discussed include: the special features, system specifications, and system design for these products; system architectures; applications for use; platforms supported; processing capabilities; memory capabilities; and targeted markets.


dependable systems and networks | 2012

Error injection-based study of soft error propagation in AMD Bulldozer microprocessor module

Cristian Constantinescu; Michael G. Butler; Chris Weller

Single-event upsets (SEU) and single-event transients (SET) may lead to crashes or even silent data corruption (SDC) in microprocessors. Error detection and recovery features are employed to mitigate the impact of SEU and SET. However, these features add performance, area, power, and cost overheads. As a result, designers must concentrate their efforts on protecting the most sensitive areas of the processor. Simulated error injection was used to study the propagation of the SEU-induced soft errors in the latest AMD microprocessor module, Bulldozer. This paper presents the Bulldozer architecture, error injection methodology, and experimental results. Propagation of soft errors is quantified by derating factors. Error injection is performed both at the module and unit level, derating factors and simulation times being compared. Accuracy is assessed by deriving confidence intervals of the derating factors. The experiments point out the most sensitive units of the Bulldozer module, and allow efficient implementation of the error-handling features.


Archive | 2008

VOLTAGE DROOP MITIGATION THROUGH INSTRUCTION ISSUE THROTTLING

Samuel Naffziger; Michael G. Butler


Archive | 2007

Multiple-core processor with hierarchical microcode store

Gene W. Shen; Bruce R. Holloway; Sean Lie; Michael G. Butler


Archive | 2008

PROCESSOR INCLUDING HYBRID REDUNDANCY FOR LOGIC ERROR PROTECTION

Michael G. Butler; Nhon Quach


Archive | 2007

MECHANISM FOR SUPPRESSING INSTRUCTION REPLAY IN A PROCESSOR

Ashutosh S. Dhodapkar; Michael G. Butler; Gene W. Shen


Archive | 2012

REPLAY REDUCTION BY WAKEUP SUPPRESSION USING EARLY MISS INDICATION

Ganesh Venkataramanan; Michael G. Butler; Krishnan Ramani


Archive | 2011

Method and apparatus for prioritizing processor scheduler queue operations

Ganesh Venkataramanan; Srikanth Arekapudi; James Vinh; Michael G. Butler


Archive | 2011

LOW OVERHEAD OPERATION LATENCY AWARE SCHEDULER

Ganesh Venkataramanan; Michael G. Butler

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Sean Lie

Advanced Micro Devices

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James Vinh

Advanced Micro Devices

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Bob Gelinas

Advanced Micro Devices

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