Michael H. Thomas

Design of ultra-low-cost UHF RFID tags for supply chain applications

The availability of inexpensive CMOS technologies that perform well at microwave frequencies has created new opportunities for automated material handling within supply chain management (SCM) that in hindsight, be viewed as revolutionary. This article outlines the system architecture and circuit design considerations that influence the development of radio frequency identification (RFID) tags through a case study involving a high-performance implementation that achieves a throughput of nearly 800 tags/s at a range greater than 10 m. The impact of a novel circuit design approach ideally suited to the power and die area challenges is also discussed. Insights gleaned from first-generation efforts are reviewed as an object lesson in how to make RFID technology for SCM, at a cost measured in pennies per tag, reach its full potential through a generation 2 standard.

A 300-MS/s 14-bit digital-to-analog converter in logic CMOS

Describes a floating-gate trimmed 14-bit 300-MS/s current-steered digital-to-analog converter (DAC) fabricated in 0.25- and 0.18-/spl mu/m CMOS logic processes. We trim the static integral nonlinearity to /spl plusmn/0.3 least significant bits using analog charge stored on floating-gate pFETs. The DAC occupies 0.44mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves better than 72-dB spur-free dynamic range at 250 MS/s.

A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25 /spl mu/m CMOS

We describe a floating-gate trimmed, 14-bit, 250 Ms/s current-steered DAC fabricated in a 0.25 /spl mu/m CMOS logic process. We trim the static INL to /spl plusmn/0.3 LSB using analog charge stored on floating-gate pFETs. The DAC occupies 0.44 mm/sup 2/ of die area, consumes 53 mW at 250 MHz, allows on-chip electrical trimming, and achieves 72 dB SFDR at 250 Ms/s.