Michael Heimlich

LNA Design Based on an Extracted Single Gate Finger Model

A GaAs low-noise amplifier (LNA) is designed with first-time success using a technique for HEMT modelling which divides the device into intrinsic gate fingers embedded in an analysable metal structure. The gate finger is characterised by de-embedding metallisation from a standard test structure. The device is then re-built, with any geometry or layout that the foundry allows, and modelled by electromagnetic (EM) analysis. This allows techniques such as asymmetric inductive source feedback in an LNA to be modelled without prior fabrication of custom test structures. The 7-13 GHz, self-biased LNA has state-of-the-art noise figure (NF) of 1.25 dB at mid-band, gain of 20.5 ± 0.1 dB with 10 dB input and output matches, 10 dBm P1dB, 14 dBm Psat and 22 dBm OIP3. Excellent agreement is achieved with simulation. In a 3x3 QFN package the measured NF is 1.36 dB and the gain is 20 dB. The first-time design success achieved here validates the modelling and parameter extraction technique.

A Broadside-Coupled Meander-Line Resonator in 0.13-

An on-chip resonator is designed and fabricated using a standard 0.13-μm SiGe technology for millimeter-wave applications. The designed resonator is based on a unique structure, which consists of two broadside-coupled meander lines with opposite orientation. The equivalent LC circuit of the resonator is given, while the impact of the structure on the resonance frequencies is investigated. Using this structure along with capacitors, a compact bandpass filter (BPF) is also designed and fabricated. The measured results show that the resonator can generate a resonance at 57 GHz with the attenuation better than 13.7 dB, while the BPF has a center frequency at 31 GHz and a insertion loss of 2.4 dB. The chip size of both the resonator and the BPF, excluding the pads, is only 0.024 mm2 (0.09×0.27 mm2).

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The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (Tj), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, Tj of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. Tj reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured Tj rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.

SiGe Technology for Millimeter-Wave Application

Gate junction temperature is presented as the crucial parameter for modeling thermal degradation in GaAs device reliability studies, and sufficient for modeling the impact of temperature on device terminal characteristics. Gate metal resistance thermometry (GMRT) is applied to a GaAs pseudomorphic high-electron mobility transistor to measure its gate junction temperature. It is found that gate leakage current due to impact ionization can interfere with dc GMRT measurements. To the best of our knowledge, for the first time it is demonstrated that this can be largely avoided by instead applying an ac version of GMRT. However, the dynamic resistance of the gate leakage current path can interfere with ac GMRT. Measurements and thermal finite element method simulations of devices at constant power dissipation conclude that the bias dependence of the channel heat source profile affects the gate junction temperature. A parameter extraction technique is presented and used in device lifetime calculations to demonstrate MTTF variations of more than an order of magnitude (despite fixed power) due to bias-dependent self-heating.

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

A higher frequency, over 2 GHz, is suggested for current 4G or 5G wideband applications. By adopting a unique gain control method, an analog-controlled variable-gain amplifier (VGA) with an accurate dB-linear characteristic is presented. The designed VGA not only features large bandwidth, but also has accurate gain adjustment with a relatively wide control voltage range. The VGA has a measured gain range of 24 dB, of which 17.3 dB is dB-linear with less than ±0.3-dB gain error. The -3-dB bandwidth is relatively constant from 2 to 2.2 GHz for the entire dB-linear range. An output 1-dB compression point of 1.8 dBm and a noise figure of 24 dB are measured. Due to the simple structure, the current consumption of the VGA core is only 2.9 mA from a 1.2-V supply, and the size is only 225 μm×45 μm, excluding pads. Moreover, the robustness of the designed VGA is verified by means of Monte Carlo simulation.

Study of Gate Junction Temperature in GaAs pHEMTs Using Gate Metal Resistance Thermometry

A compact balanced frequency doubler with more than 35 dB odd-harmonic rejection and fractional bandwidth of 73% is presented in this letter. Wide bandwidth and high odd-harmonic suppression is achieved by adopting a new technique for the transformer balun design, resulting in a very low magnitude imbalance of 0.13 dB and a phase imbalance of 0.4° over 7-15 GHz. The balun performance is improved by offsetting the radius of the primary and secondary coils, which reduces the parasitic coupling capacitance. The input and output frequency ranges for the doubler are 7-15 GHz and 14-30 GHz respectively. The circuit was fabricated in 0.13-μm SiGe technology. The chip size is 0.6 mm × 0.4 mm.

A Wideband Analog-Controlled Variable-Gain Amplifier With dB-Linear Characteristic for High-Frequency Applications

A GaAs pHEMT frequency doubler, a quadrupler and a power amplifier for E-band applications have been demonstrated to achieve useful output power and power added efficiency (PAE) over a wide bandwidth. The doubler and quadrupler circuits include medium power amplifiers to increase their gain and output power. The doubler has a measured output power greater than 15 dBm over the entire 15 GHz bandwidth of the European Telecommunications Standards Institute (ETSI) E-band specification. The quadrupler has similar output power over the ETSI E bands with a maximum output power of 19.2 dBm. The power amplifier has a maximum measured output power of 24.2 dBm (265 mW) and exceeds 23 dBm (200 mW) over the ETSI E bands. This amplifier has a measured small signal gain of 15 dB and the input and output return losses exceed 15 dB. Its measured PAE is above 8% across the ETSI E bands. This is the highest saturated output power (Psat) and PAE for a power amplifier spanning the full 71 to 86 GHz span of the ETSI E bands for any semiconductor system. Good agreement is demonstrated between measurement and simulation.

A

An ultra-compact integrated resonator and bandpass filters (BPF), in silicon-based technology, are presented for millimetre-wave applications. The resonator consists of two broadside-coupled lines in opposite orientations. Using this resonator, a first-order and a second-order BPFs were also designed. To prove the concept, three prototypes of each of the resonator and the first-order BPF were fabricated using a standard 0.13-μm SiGe process. The measured results show that the resonator has an attenuation of 13.7 dB at the resonance frequency of 57 GHz, while the BPF has a centre frequency of 31 GHz and an insertion loss of only 2.4 dB. Excluding the pads, the chip size of both the resonator and the BPF is extremely compact, only 0.024 mm2 that is equivalent to 0.001 λg2. The unloaded Q factor of the filter is higher than other state-of-the-art designs.

K

A transformer-coupled frequency quadrupler with 50% bandwidth is designed in a 0.25μm SiGe process. The quadrupler covers an output frequency range from 36GHz to 60 GHz with a total power consumption of 38.5mW for a supply voltage of 2.5V. To fulfil the requirement of harmonic suppression, a novel on-chip asymmetrical Marchand balun structure is adopted to compensate the phase and amplitude errors across a wide bandwidth, so that the 3rd- and 5th harmonic suppressions of more than 30-dB can be achieved. The transformer-coupled approach along with a common-base configuration is adopted to enlarge the bandwidth of the multiplier.

-Band Frequency Doubler With 35-dB Fundamental Rejection Based on Novel Transformer Balun in 0.13-

This paper presents improvement technique on linearity of a CMOS double balance Gilbert cell mixer with considerable high conversion gain at low power consumption. The mixer consists of inductive source degeneration in the transconductance stage providing impedance matching to improve linearity of the mixer. The mixer was designed to operate a Radio Frequency (RF) signal of 4GHz, a Local Oscillator frequency (LO) of 3.75GHz, thus providing an Intermediate Frequency (IF) of 0.25GHz. The circuit presents an Input third order Intercept point (IIP3) of +1dBm. A conversion gain of 10.45dB and a single sideband noise of 8dB over the band width. The DC power consumed by the core mixer is 4.5mW. The proposed active mixer design was made in 0.25μm CMOS Silanna process, suitable for wideband applications.