Sayed Ali Albahrani

Identifying a Double-Energy-Level Trap Center in a GaN HEMT by Performing Three-Stage Pulse Measurements

The results of measurements performed on a GaN high electron-mobility transistor (HEMT) by two different pulse-measurement techniques are presented. By performing two-stage pulse measurements, two distinct current-injection mechanisms responsible for triggering the trapping process are identified. By performing three-stage pulse measurements, the trap center at which the trapping process occurs is identified to be a double-energy-level trap center, which is a trap center with two distinct energy levels between which there is an interaction. This result has a significant impact on the design of more accurate large signal models for GaN HEMTs.

Three-stage pulse measurement technique for characterization of charge trapping in FETs

A difficulty concerning characterization of charge trapping in microwave FETs by performing pulse measurements is the possible overlap between the trapping and self-heating rates. Another difficulty is that the potential introduced by charge trapping modulates the drain-source current differently at bias points with different values of drain-source conductance, gm, and drain transconductance, gd. Measurement of true-DC values for gm and gd at all bias points will then be required for estimating the potential introduced by charge trapping. For devices such as GaN HEMTs, true-DC values for gm and gd at each bias point can be obtained only after thousands or tens of thousands of seconds after pulsing the device. A new pulse-measurement technique is proposed that overcomes these difficulties. The results of measurements performed on a GaN HEMT using the proposed pulse-measurement technique is presented, and the observed trapping behavior is characterized.

Trap model for GaN RF HEMT power switch

RF GaN HEMTs were characterized as power switches using pulsed IV system. The devices exhibited current collapse and ON resistance modulation. These trap effects were highly dependent on off state quiescent drain bias voltages. At higher switch voltages, the output power was reduced due increase in the ON resistance and collapse of drain current. Traps located on the surface between gate and drain caused RON modulation while the traps in the bulk beneath the gate plate caused current collapse. A power HEMT model incorporating traps was developed and simulations correctly predicted knee walk out due to increase in the ON resistance and current collapse due to bulk traps.

Study of self-heating in GaAs pHEMTs using pulsed I-V Analysis

A pulsed I-V thermal resistance Rth measurement method is formulated and applied on-wafer to a GaAs MMIC pHEMT. An investigation of device dispersion phenomena assesses their impact on the measurement. It is found that performing the Rth measurement using two quiescent bias points in close proximity (situated beyond the knee voltage yet prior to drain voltages that result in significant levels of gate leakage due to impact ionization) improves the accuracy of the method. Extraction of thermal coefficients characterizes the drain current reduction due to heating, allowing for an efficient calculation of Rth with improved precision.

Characterization of trapping and thermal dispersion in GaN HEMTs

Dispersion in a GaN HEMT, including gate and drain lag, is related to a new trapping model based on SRH theory. Measurements and SPICE simulation are used to verify the capability of this model to explain the bias-and terminal-potential dependency of the turn-on transients and their time constants. The models of both drain current and trapping need to consider temperature and power dissipation versus time. The interaction between two different trap mechanisms and two different self-heating processes is shown to adequately explain the different characteristics of the turn-on transient of the transistor under test.

Iso-Trapping Measurement Technique for Characterization of Self-Heating in a GaN HEMT

The temperature response of field-effect transistors (FETs) to instantaneous power dissipation has been shown to be significant at high frequencies, even though the self-heating process has a very slow time constant. This affects intermodulation at high frequencies. A major difficulty in characterizing the self-heating process in microwave FETs is to differentiate between the self-heating and charge-trapping rates. An iso-trapping measurement technique is proposed by which it becomes possible to characterize the self-heating process in an FET in isolation from the effect of the charge-trapping process in the FET. The results of iso-trapping measurements performed on a GaN high-electron-mobility transistor are presented, and used to successfully characterize the self-heating process.

GaAs MMIC pHEMT gate metal thermometry

A thermal resistance measurement technique which exploits the thermal response of a GaAs pHEMTs gate metal resistance is examined. It is found that gate leakage (hole) current due to impact ionization can interfere with the measurement, but can be avoided with correct choice of bias. Measurements and thermal simulations conclude that the bias dependence of the channel heat source profile needs to be considered to improve the accuracy of channel temperature estimation.

Circuit Model for Double-Energy-Level Trap Centers in GaN HEMTs

Measurement results performed on a GaN high-electron-mobility transistor that show the presence of a double-energy-level (DEL) trap center in the device are presented. A novel, yet simple, circuit implementation of a DEL trap center in an FET is presented that is immediately extendableto a trap centerwithmore than two energy levels. The model is based on the Shockley–Read–Hall statistics of the trapping process. The implementation is suitable for both time-domain and harmonic-balance simulations. Simulation results validate the proposed model.

SRH based trap model for GaN MMIC power switches

Gallium Nitride (GaN) HEMTs have increasingly been used in high frequency switching power converters. The combination of high voltage, high current, high temperature and low-on resistance enables higher efficiency and lower form factor as compared to Silicon devices. FET switch operate in the linear ohmic region. However, the presence of trap centres in GaN HEMTs alter the on-resistance and shifts the threshold voltage, causing current collapse and degrades the efficiency. Pulsed I-V measurements of a commercial foundry GaN MMIC HEMT revealed drain current collapse and on-resistance modulation in the ohmic region of the HEMT loadline. A trap model based on SRH theory was used to characterize trapping effects that alter the drain current in the linear region of operation.

Impact of the pulse-amplifier slew-rate on the pulsed-IV measurement of GaN HEMTs

The influence of the non-ideal response of the pulse-amplifier on the trap and self-heating dynamics, and hence, on the drain-current transient in a GaN HEMT is studied with new trap and self-heating models. It is shown that the study of the trap and self-heating dynamics requires a proper correction technique that accounts for the change in trap-potential, trap time-constant and thermal response due to the non-ideal response of the pulse-amplifier. Several post-measurement data correction techniques are discussed and shown to be incapable of predicting the true drain-current transient. A pre-measurement terminal correction technique using a new version of the pulse measurement system is used to solve the problem.