Bryan K. Schwitter

Impact of Bias and Device Structure on Gate Junction Temperature in AlGaN/GaN-on-Si HEMTs

The thermal impact of device bias-state and structures (such as source connected field plates, gate-pitch, back-vias, and number of gate fingers) in AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) are measured using gate metal resistance thermometry (GMRT). The technique characterizes the thermal response of device gate metallization to determine the gate-epilayer junction temperature (Tj), which is directly influenced by the channel heat source due to its close proximity. It is found that low gate leakage levels in GaN HEMTs make them favorable candidates for GMRT. Bias-dependent self-heating, independent of power dissipation, is observed in the devices. Therefore, Tj of different device configurations are compared at constant bias state, as well as constant power density (3.75 W/mm) to improve accuracy. Tj reduction is observed at high drain bias due to the migration of the channel heat source toward the gate field plate edge. This provides independent experimental validation for a reported electrothermal model [7]. A 3-D thermal finite element method model is presented, which simulates measured Tj rise to within ~6% across a range of device configurations and operating conditions. This is ultimately made possible upon implementation of a thermal boundary resistance layer and extraction of its temperature response using GMRT data.

Study of Gate Junction Temperature in GaAs pHEMTs Using Gate Metal Resistance Thermometry

Gate junction temperature is presented as the crucial parameter for modeling thermal degradation in GaAs device reliability studies, and sufficient for modeling the impact of temperature on device terminal characteristics. Gate metal resistance thermometry (GMRT) is applied to a GaAs pseudomorphic high-electron mobility transistor to measure its gate junction temperature. It is found that gate leakage current due to impact ionization can interfere with dc GMRT measurements. To the best of our knowledge, for the first time it is demonstrated that this can be largely avoided by instead applying an ac version of GMRT. However, the dynamic resistance of the gate leakage current path can interfere with ac GMRT. Measurements and thermal finite element method simulations of devices at constant power dissipation conclude that the bias dependence of the channel heat source profile affects the gate junction temperature. A parameter extraction technique is presented and used in device lifetime calculations to demonstrate MTTF variations of more than an order of magnitude (despite fixed power) due to bias-dependent self-heating.

Steady state and transient thermal analyses of GaAs pHEMT devices

GaAs pHEMT thermal reliability test structures are introduced which incorporate on-wafer heating using Thin Film Resistors (TFR) and a DC gate metal temperature measurement method. Results from 3D Finite Element Method (FEM) thermal simulations are compared with measurements and used to investigate the frequency response of device self-heating. Comparisons are made with existing thermal models. The influence of individual device structures on the thermal characteristics of an entire device is investigated and the epitaxial layers are seen to have a large impact on overall performance. Bias dependent self-heating, independent of thermal dissipation is observed and attributed to confinement of the thermal source as the drain voltage is increased.

An Integrated Electrothermal Design Primer Using an SiGe HBT PA [Application Notes]

The integrated design flow that links simulation, layout, and electromagnetic (EM) analysis is the foundation for modern RF/microwave integrated circuit (IC) design. The inclusion of thermal simulation in this flow is now possible with modern thermal solvers linked into RF/microwave integrated design tools. Silicon germanium (SiGe) heterojunction bipolar transistor (HBT) power amplifier (PA) design is used as an example where such a flow is most beneficial due to numerous issues such as array sizing and thermal runaway. An electrothermal flow is discussed relative to some overall metrics for design flows and that incorporates the availability of an integrated thermal solver into the earliest parts of, and potentially throughout, the entire design flow. The result is a flow that potentially reduces iterations during the design process and boosts design performance by freeing up margin.

AlGaN/GaN HEMT nonlinear model fitting including a trap model

A procedure for the extraction of a trap model is applied to an AlGaN/GaN-on-SiC HEMT. The trap model is then used in the extraction of a nonlinear device model. The resulting model accurately relates dc I-V with nonlinear behaviour which is crucial for accurately predicting the load-pull measurements. This modeling procedure can be integrated into a modelling/design flow enabling accurate prediction of device and circuit performance.

Parameter Extractions for a GaAs pHEMT Thermal Model Using a TFR-Heated Test Structure

The temperature-dependent thermal conductivities of a GaAs pseudomorphic high-electron mobility transistors (pHEMT) substrate and epilayer regions are extracted to develop a 3-D finite-element-method thermal model. The thermal characterization is based on electrical gate-metal-finger temperature measurements of a customized GaAs pHEMT test structure. Heat flow from an integrated thin-film resistor is shown to be sensitive to the devices substrate thermal conductivity, while heat flow from the devices channel is most significantly affected by the epilayer region thermal conductivity. These observations are used in the formulation of the thermal parameter extraction technique, which serves as a useful and convenient device modeling tool that can be integrated into an engineering design flow. Specific knowledge about the semiconductor material fabrication process, which may be unavailable to the design engineer, is not required for accurate thermal characterization; this is the overriding advantage of the technique presented.

Study of self-heating in GaAs pHEMTs using pulsed I-V Analysis

A pulsed I-V thermal resistance Rth measurement method is formulated and applied on-wafer to a GaAs MMIC pHEMT. An investigation of device dispersion phenomena assesses their impact on the measurement. It is found that performing the Rth measurement using two quiescent bias points in close proximity (situated beyond the knee voltage yet prior to drain voltages that result in significant levels of gate leakage due to impact ionization) improves the accuracy of the method. Extraction of thermal coefficients characterizes the drain current reduction due to heating, allowing for an efficient calculation of Rth with improved precision.

Iso-Trapping Measurement Technique for Characterization of Self-Heating in a GaN HEMT

The temperature response of field-effect transistors (FETs) to instantaneous power dissipation has been shown to be significant at high frequencies, even though the self-heating process has a very slow time constant. This affects intermodulation at high frequencies. A major difficulty in characterizing the self-heating process in microwave FETs is to differentiate between the self-heating and charge-trapping rates. An iso-trapping measurement technique is proposed by which it becomes possible to characterize the self-heating process in an FET in isolation from the effect of the charge-trapping process in the FET. The results of iso-trapping measurements performed on a GaN high-electron-mobility transistor are presented, and used to successfully characterize the self-heating process.

Transient gate resistance thermometry demonstrated on GaAs and GaN FET

The development of transient gate resistance thermometry (T-GRT) is reported. It is a technique used to measure the transient self-heating of a FETs gate metal. Demonstrations of T-GRT are presented at the wafer level on a GaAs pHEMT and an AlGaN/GaN-on-SiC HEMT. Dynamic self heating is monitored from hundreds of nanoseconds to hundreds of milliseconds. Preliminary finite-element simulations across a range of power dissipation levels agree closely with T-GRT at, and beyond, 1 μs after the applied drain pulse. Characterization of dynamic self heating and its application to pulsed applications such as radar are discussed.

Thermal modelling of multifinger GaAs/GaN FETs using SPICE

A simple thermal model is presented to estimate the junction temperature in multi-finger GaAs and GaN high electron mobility transistors (HEMTs). The model is implemented in SPICE by treating heat flow as analogous to the flow of electric current. The model enables a comprehensive study of different layout possibilities for devices. Results from 3D Finite Element Model (FEM) simulation and from Gate Metal Resistance Thermometry (GMRT) are compared with the model.