Michael Higgins

SoCECT: System on Chip Embedded Core Test

This paper presents SoCECT (system on chip embedded core test), a novel test controller architecture that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. SoCECT makes use of the IEEE 1149.1 JTAG state machine to operate the test controller and also to allow for future integration with an IEEE P1687 interface. SoCECT also includes a test access mechanism (TAM) methodology(distributed architecture) that reuses the physical connections of the SoC system bus to provide an efficient transport medium for structural and functional test vectors between the embedded test controller and IEEE 1500 wrapped cores.

Design and implementation challenges for adoption of the IEEE 1500 standard

The IEEE 1500 standard for embedded core test, approved in 2005, defines a scalable and reusable wrapper architecture that allows the testing of, and access to, embedded cores within a system on chip (SoC). The wrapper is controlled using a Wrapper Instruction Register (WIR), and has serial and parallel ports for test access mechanisms (TAMs) to deliver test vectors to the cores under test. In this study, the authors consider two implementation challenges that are outside the IEEE 1500 standard: how multiple WIRs within a SoC are controlled and accessed and also the TAM architecture. The authors present novel solutions to both challenges in the form of a test controller to interface with the embedded IEEE 1500 structures and also a TAM architecture that reuses the physical interconnections of an on-chip system bus. The test controller facilitates concurrent test of multiple IEEE 1500 wrapped cores in an SoC through the IEEE 1149.1 test access port (TAP). Reusing the physical interconnections of the system bus as a TAM is not dependent on the system bus protocol or functionality.

IEEE 1500 Core Wrapper Optimization Techniques and Implementation

IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.

A Novel System on Chip (SoC) Test Solution

A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a test access mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.

SoC Test: Trends and Recent Standards

The well-known approaching test cost crisis, where semiconductor test costs begin to approach or exceed manufacturing costs has led test engineers to apply new solutions to the problem of testing System-On-Chip (SoC) designs containing multiple IP (Intellectual Property) cores. While it is not yet possible to apply generic test architectures to an IP core within a SoC, the emergence of a number of similar approaches, and the release of new industry standards, such as IEEE 1500 and IEEE 1450.6, may begin to change this situation. This paper looks at these standards and at some techniques currently used by SoC test engineers. An extensive reference list is included, reflecting the purpose of this publication as a review paper.