Brendan Mullane

SoCECT: System on Chip Embedded Core Test

This paper presents SoCECT (system on chip embedded core test), a novel test controller architecture that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. SoCECT makes use of the IEEE 1149.1 JTAG state machine to operate the test controller and also to allow for future integration with an IEEE P1687 interface. SoCECT also includes a test access mechanism (TAM) methodology(distributed architecture) that reuses the physical connections of the SoC system bus to provide an efficient transport medium for structural and functional test vectors between the embedded test controller and IEEE 1500 wrapped cores.

Design and implementation challenges for adoption of the IEEE 1500 standard

The IEEE 1500 standard for embedded core test, approved in 2005, defines a scalable and reusable wrapper architecture that allows the testing of, and access to, embedded cores within a system on chip (SoC). The wrapper is controlled using a Wrapper Instruction Register (WIR), and has serial and parallel ports for test access mechanisms (TAMs) to deliver test vectors to the cores under test. In this study, the authors consider two implementation challenges that are outside the IEEE 1500 standard: how multiple WIRs within a SoC are controlled and accessed and also the TAM architecture. The authors present novel solutions to both challenges in the form of a test controller to interface with the embedded IEEE 1500 structures and also a TAM architecture that reuses the physical interconnections of an on-chip system bus. The test controller facilitates concurrent test of multiple IEEE 1500 wrapped cores in an SoC through the IEEE 1149.1 test access port (TAP). Reusing the physical interconnections of the system bus as a TAM is not dependent on the system bus protocol or functionality.

A2DTest: A complete integrated solution for on-chip ADC self-test and analysis

An on-chip BIST solution performing accurate ADC measurements is presented. The platform enables linear and dynamic testing to occur in parallel, significantly lowering test time and cost. On-chip hardware resources are optimized for ADC test application.

An on-chip solution for static ADC test and measurement

This paper presents a solution for implementing low-cost ADC BIST into a System-on-Chip design. The solution is based on generating a programmable ramp as a test signal into the ADC and measuring the linear parameters using the histogram based test. An original approach for accurately measuring the Hits-per-Code as the ramp traverses the ADC transfer curve is presented. In particular, it is shown that code transitions or code flicker noise have an impact on the overall accuracy. This test procedure permits a ramp generator implementation and test engine design that is predominantly a digital solution. Results demonstrate lower silicon area overheads and lower test time capability.

A high performance band-pass DAC architecture and design targeting a low voltage silicon process

Direct Digital Synthesis (DDS) systems generate adjustable high resolution phase and frequency signals that are used in a wide variety of applications such as multi-mode RF, communications, measurements and test. A high performance band-pass DAC architecture and implementation is presented that delivers high spectral purity over a narrow-band response. The low power DAC is portable to standard CMOS processes and achieves 110dB narrowband SFDR performance using sigma-delta (µΔ) modulation and multi-bit current steering techniques. A 3rd order digital µΔ modulator is combined with a 4th order digital Dynamic Element Matching (DEM) block to shape the noise while calibrating for process mismatch variations. A low silicon area output stage is used to deliver a high performance specification.

A prototype platform for system-on-chip ADC test and measurement

An optimal solution for implementing ADC Built-In-Self-Test into a SOC design is presented. ADC linear and dynamic testing occurs in parallel which reduces test time. A signal generator produces a ramp for linear histogram measurements and a sine-wave signal for dynamic tests. This platform permits a BIST design that is predominantly a digital solution and enables accurate testing using low silicon area.

IEEE 1500 Core Wrapper Optimization Techniques and Implementation

IEEE 1500 core wrappers supporting a hybrid scan mode provide for lower test times with minimal wiring and logic overheads. Wrapper logic and vector formats that are easily integrated with modern IC/FPGA design flows are demonstrated.

A Novel System on Chip (SoC) Test Solution

A novel test controller architecture is presented that allows multiple IEEE 1500 wrapped cores within a SoC to be tested concurrently. The IEEE 1149.1 state machine is used to interface to the test controller allowing potential integration with the emerging IEEE P1687 (IJTAG) standard. Also included is a test access mechanism (TAM) methodology that reuses the physical connections of the SoC system bus to provide an efficient transport medium for test vectors between the test controller and IEEE 1500 wrapped cores.

High order mismatch noise shaping for bandpass DACs

This paper presents a stable 4th order mismatch shaping technique using vector feedback dynamic element matching (DEM). When combined with a multi-bit sigma delta modulator, this DEM system allows high resolution band pass signals to be produced, using a low resolution unary weighted DAC.

An SOC platform for ADC test and measurement

An Analog to Digital Converter Built-in-Self-Test design for System-on-Chip applications is presented. Linear and dynamic ADC test occur in parallel to reduce overall test time. A ramp generator is used for linear histogram measurements and a sine-wave signal is applied for dynamic tests. The design precisely measures Hits-per-Code enabling accurate linearity test and a low-area optimal CPU operates dynamic measurements. Results demonstrate efficient silicon area overheads and lower test time capability.