Michael Hsu

65-nm full-chip implementation using double dipole lithography

Double Dipole Lithography (DDL) has been demonstrated to be capable of patterning complex 2D patterns. Due to inherently high aerial imaging contrast, especially for dense features, we have found that it has a very good potential to meet manufacturing requirements for the 65nm node using ArF binary chrome masks. For patterning in the k1<0.35 regime without resorting to hard phase-shift masks (PSMs), DDL is one unique Resolution Enhancement Technique (RET) which can achieve an acceptable process window. To utilize DDL for printing actual IC devices, the original design data must be decomposed into “vertical (V)” and “horizontal (H)” masks for the respective X- and Y-dipole exposures. An improved two-pass, model-based, DDL mask data processing methodology has been established. It is capable of simultaneously converting complex logic and memory mask patterns into DDL compatible mask layout. To maximize the overlapped process window area, we have previously shown that the pattern-shielding algorithm must be intelligently applied together with both Scattering Bars (SBs) and model-based OPC (MOPC). Due to double exposures, stray light must be well-controlled to ensure uniform printing across the entire chip. One solution to minimize stray light is to apply large patches of solid chrome in open areas to reduce the background transmission during exposure. Unfortunately, this is not feasible for a typical clear-field poly gate masks to be patterned by a positive resist process. In this work, we report a production-worthy DDL mask pattern decomposition scheme for full-chip application. A new generation of DDL technology reticle set has been developed to verify the printing performance. Shielding is a critical part of the DDL. An innovative shielding scheme has been developed to protect the critical features and minimize the impact of stray light during double exposure.

Eigen-decomposition-based models for model OPC

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable optical lithography tackling 45nm node and beyond. To meet the challenges imposed by the previously unthinkable low k1 for manufacturing with most stringent dimension control requirements, a capable model OPC to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new model OPC must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, such as customer designed illuminator and experimental measured illuminator profile from the scanners. This capability is very important since the real illuminator pupil can impact OPC accuracy. The physical and mathematical foundation of the model must be well thought of to meet the requirement for the above-mentioned applications. We have developed a novel Eigen Decomposition Model (EDM) for model OPC treatment applicable for all types of advanced binary and phase-shifting masks. Together with a full 2D model calibration and verification methodology, the results from this new model OPC have proven to achieve a superb CD accuracy with versatile capabilities for extreme low k1 imaging application. This report will explain how the model works with example applications and actual wafer results.

Improvement of lithography process by using a FlexRay illuminator for memory applications

As is well recognized, source mask optimization (SMO) is a highly effective means of extending the lifetime of a certain photolithography generation without an expensive upgrade to the next generation optical system. More than an academic theory, source optimization first found practical applications in the debut of the pixel-like programmable illuminator in 2009 for producing near freeform illumination. Based on programmed illumination, related studies have demonstrated a nearly identical optical performance to that generated by the conventionally adopted diffractive optical element (DOE) device without the prolonged manufacturing time and relatively high cost of stocking up various DOEs. By using a commercially available pixel-like programmable illuminator from ASML, i.e. the FlexRay, this study investigates the effectiveness of FlexRay in enhancing image contrast and common process window. Before wafer exposure, full SMO and source-only (SO) optimization are implemented by Tachyon SMO software to select the optimum illumination source. Wafer exposure is performed by ASML XT:1950i scanner equipped with a FlexRay illuminator on a critical layer of DRAM process with known hotspots of resist peeling. Pupil information is collected by a sensor embedded in the scanner to confirm the produced source shape against the programmed source and the optically simulated CD. When the FlexRay illuminator is used, experimental results indicate that lithography hotspots are eliminated and depth of focus is improved by as much as 50% in comparison with those from a traditional AERIAL illuminator. Regular focus-exposure matrix (FEM) and the subsequent critical defects scanning reveal that the common process window of the tight-pitched array and the periphery can be enhanced simultaneously with no hotspot identified. Therefore, a programmed source is undoubtedly invaluable in terms of additional manufacturing flexibility and lower cost of ownership when attempting to improve product yield in high volume production.

RET integration of CPL technology for random logic

As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.

Low k1 lithography patterning option for the 90-nm and 65-nm nodes

As IC fabrication processes are maturing for the 130nm node, silicon manufacturers are focusing on 90nm device manufacturing at ever-lower k1 factors. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at similar k1 near 0.3. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique. For low-volume, the high mask cost of Alt-PSM discourages its use. What are the most sensible KrF lithography patterning options at k1 = 0.3? For single exposure mask solutions at the 90nm node using KrF, there are two leading candidates: 6% attenuated PSM (Att-PSM) and Chromeless Phase Lithography (CPL). In this work, we explored and compared these two options in terms of the best achievable process latitude for patterning poly gate layer. First, we analyzed the diffraction patterns from 6% Att-PSM and CPL mask features and identified the optimum transmission for various pitches. Next, we examined the two options from a mask making perspective, accessing mask manufacturability, phase and transmission error control, defect sources, etc. In this paper, we describe how hybrid CPL can be used as a variable transmission mask to produce the best through pitch imaging performance and a practical implementation method for mask manufacturing.

Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

RET masks for patterning 45nm node contact hole using ArF immersion lithography

Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process. In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks. To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.

Manufacturing implementation of IML technology for 45 nm node contact masks

For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RETs beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k1 for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

Full-chip manufacturing reliability check implementation for 90-nm and 65-nm nodes using CPL and DDL

Advanced masks such as CPL and DDL are the two leading low k1 lithography enablers for the upcoming 90nm and 65nm nodes. The mask generation methodologies for both have been clearly defined with convincing wafer printing results. We found that full-chip optical proximity correction (OPC) is by all means one of most critical components for CPL and DDL. The OPC process ensures the correct 2D pattern shapes and to achieve the desired CD to be printed on wafer with sufficient process margin. However, in addition to the already complex mask data generation, the OPC process further increases mask data complexity and more prone to data handling errors. It is therefore highly desirable to perform full-chip Manufacturing Reliability Check (MRC) prior to mask making. From our viewpoints, MRC needs to cover two goals: first is to single out the “weak printing spots” or to map out the treated CPL/DDL features with unacceptable DOF and exposure latitude so that the corrective actions can be taken, and second is to ensure printing of the entire chip to meet the process requirement. The success of MRC process depends on a well-trained modeling algorithm, which should be well capable of predicting the optical and resist behavior correctly across the entire chip. To perform a production worthy MRC for CPL (with two mask writing steps) and DDL (with two exposure masks), one must have a full knowledge of the mask generation principles for both. In this paper, we demonstrate a working scheme that has been designed to capture a variety of geometric variations on the treated mask layout that could lead to unacceptable printing performance. In this scheme, the MRC for CPL and DDL are handled in two separate modules and the final MRC data is characterized and classified into specified category. The predicted error points were reported and displayed through statistical analysis. Process tolerance during mask making was also taking into consideration. For the optimum MRC performance, we try to balance the wafer pattern fidelity, data complexity, and the mask cost. The fix suggestions for the failure discovered can be automatically proposed for some of specified layouts. This MRC method could also be applied to all types of PSM or multi-exposure mask.

OPC model calibration for CPL patterning at extreme low k1

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable the low k1 optical lithography. To meet the challenges imposed by the previously unthinkable low k1 for manufacturing with most stringent dimension control requirements, a capable OPC model to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new OPC model must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, usch as customer designed illuminator and experimental measured illuminator profile from the scanners. The physical and mathematical foundation of the model must be well thought of to meet the requirements for the above-mentioned applications. We have extended our Eigen Decomposition Model (EDM) for model OPC treatment into the high NA regime, in which the vector characteristics of light and thin film stack are taken into account. For CPL calibration, it has been found that 3D mask topography effect cannot be ignored in order to achieve satisfactory model accuracy.