Michael Jackson

Microelectronic engineering at RIT-10 years of industry partnership

The microelectronic engineering program at Rochester Institute of Technology (RIT) is the only ABET accredited B.S. Microelectronic Engineering program in the United States. The program requires co-op, making it five years in length. Co-op students alternate six months of co-op employment with six months of school. Currently 250 students are in the program and more than 300 graduates are employed (mostly as process engineers) at semiconductor manufacturing locations nationwide. The undergraduate and graduate curricula are discussed. A description of the laboratory facility is included.<<ETX>>

25 Years of Microelectronic Engineering Education

Rochester Institute of Technology started the nations first Bachelor of Science program in Microelectronic Engineering in 1982. The program has kept pace with the rapid advancements in semiconductor technology, sharing 25 of the 40 years characterized by Moores Law. The program has constantly advanced its integrated circuit fabrication laboratory in order to graduate students with state-of-the-art knowledge, who become immediate and efficient contributors to their company or graduate program. Today, this facility serves as a key resource for research in semiconductor devices, processes, MEMS, nanotechnology, and microsystems. This has led to the creation of the first PhD program in engineering at RIT, a Doctorate in Microsystems Engineering. The department enjoys strong support from the semiconductor industry through its industrial affiliate program. Recently the department received a

Microelectronic engineering education for emerging technologies

1 million department level reform grant to address the imminent need for a highly educated workforce for the US high tech industry that is on the verge of nanotechnology revolution.

A 2000 transistor p-well CMOS gate array a vehicle for microelectronics manufacturing education

The Department of Microelectronic Engineering at Rochester Institute of Technology received NSF Department Level Reform (DLR) planning and implementation grants in 2003–04 and 2005–10, respectively. The primary mission of these efforts was to evaluate and develop educational initiatives towards nanotechnology aligned with recommendations from the institution of National Nanotechnology Initiatives published by the US Government in 2000. The Department proposed to take this opportunity further and guide its curriculum toward new frontiers in nanotechnology and micro-electro-mechanical systems (MEMs). Advances in semiconductor technology have resulted in micro/nanofabrication techniques being employed in MEMs, chemical & bio sensors, and in energy harvesting devices and systems. The technology has evolved through aggressive process control and scalability characterized by Moores Law. The result has been emergence of a multifunctional “More than Moore” regime that is increasingly multidisciplinary in nature. Under this effort, new courses and curricula in Microelectronics and Nanofabrication providing access to state-of-the art semiconductor fabrication facilities to students from different science and engineering programs have been formulated.

Work in progress — Integrating semiconductor and nanotechnology fundamentals into a high school science curriculum module

A 2000 transistor p-well CMOS gate array has been designed for use as a teaching tool in the microelectronic engineering program at RIT. Students in microelectronic engineering study integrated circuit design and integrated circuit manufacturing starting in the first year of the five year program. The gate array is manufactured up to level 8 of the 11 level process by students in 5th year manufacturing classes. Levels 8 through 11 include contact cut, metal-one, via and metal-two. These levels are where the gate array is customized. The first year students design simple digital circuits, learn about schematic capture, simulation, bread boarding and layout. They also complete the wafer fabrication as part of their laboratory experience Students in more advanced courses design more complex analog and digital circuits to be realized using the 2000 transistor gate array. The gate array project has provided an interesting educational experience in design, layout and manufacturing for students from freshmen year to graduate level. The device turn around time is about one week for the last 4 levels of the process.

Excelsior scholars summer program: Introducing K-12 students to microelectronic and nanofabrication through photovoltaics

The Microelectronic Engineering Faculty at Rochester Institute of Technology have been engaged in two day K-12 Teacher forums addressing the engineering and fabrication of semiconductor devices for 12 years. A common theme that has emerged is the difficulty teachers have introducing new topics, such as those presented at the above-mentioned forums, to their students. It has become apparent to the Microelectronic Engineering faculty that a pre-developed curriculum requiring only teacher training would have the best chance of making a major impact. This paper reports on work in progress on a five week module designed to introduce semiconductor and nanotechnology fundamentals to AP physics students during the time after their AP exam in May and graduation in June. A major benefit of such a program would be introducing STEM students to exciting career opportunities.

K-12 teachers forum on microelectronics and nanotechnology

A two week summer camp for 7th–8th grade students introducing the attendees to modern integrated circuit manufacturing through basic solar cell fabrication has been developed and delivered. The program was funded by New York State Department of Education and challenged the grantee to develop a camp that would engage these middle school students in science activities at a level commensurate with high school graduation learning outcomes. An independent evaluator performed a rigorous evaluation using multiple methods, to triangulate the findings. The results showed the program was implemented with fidelity to the grant proposal and that high quality instructional strategies were used. Students exhibited a statistically significant increase in positive attitudes toward science and in self-efficacy for doing science. Details on camp agenda, hands-on activities, staffing, logistics, student recruitment, and budget are discussed for those considering similar activities.

Development and characterization of 10 nm, N/sub 2/-implanted nitrided oxides for gate dielectrics

The Microelectronic Engineering Department at Rochester Institute of Technology (RIT) has developed a K-12 Outreach Forum on Microelectronics and Nanotechnology that was delivered to 16 teachers in November of 2006, and again in November of 2007 (Jackson, et.al., 2007). A spring session for March 2008 is already filling, so the response from the K-12 community has been overwhelming.

Development of techniques to monitor and control minority carrier lifetime in silicon to improve yields in a university fab

A 20 nm, Al-gate SiO/sub 2/ MOS capacitor process exists at Rochester Institute of Technology (RIT) which produces yields /spl ges/90% for a performance spec of /spl ges/9 MV/cm field strength for dielectric breakdown. Scaling the dielectric thickness down below 10 nm resulted in a corresponding decrease in dielectric strength performance with 8 nm films exhibiting mean dielectric strength values of only 2 MV/cm, An increase in leakage currents accompanies this degradation in dielectric integrity. Switching to a polysilicon gate for sub 20 nm oxides restores the dielectric strength performance, but the additional levels of processing associated with LOCOS and polysilicon gates is not conducive to rapid evaluation of dielectric integrity. A nitrided oxide, formed by ion implantation, has been shown to result in mean dielectric strength values /spl ges/9 MV/cm for Al-gate MOS capacitors with dielectric thicknesses down to 10 nm. Preliminary XPS data indicates that the nitrided film is more resistant to defect formation, and this may explain the enhanced performance.

Introduction of a surface charge analysis instrument into the microelectronic engineering curricula at the Rochester Institute of Technology

Measurement of minority carrier lifetime (/spl tau/), either indirectly via pn diode leakage current or directly from MOS capacitors, is used as a monitor to detect and correct contamination in an university fab. Diodes fabricated utilizing an internal gettering process exhibited improvements in leakage current levels about the wafer center when compared with diodes fabricated sans gettering, indicating the possibility of contamination by outdiffusion of impurities from the tube walls. Surface charge analysis (SCA) of an oxidized silicon wafer detected a 30% decrease in /spl tau/ over a 6 hr N/sub 2/ anneal in the tube used for gettering. The same experiment conducted in a tube contaminated with Zn yielded a 45% drop in lifetime. Both gas sources and RCA clean chemistry are being investigated as possible contamination sources of the getter tube.