Michael James Paisley

Techniques for Minimizing the Basal Plane Dislocation Density in SiC Epilayers to Reduce Vf Drift in SiC Bipolar Power Devices

Forward voltage instability, or Vf drift, has confounded high voltage SiC device makers for the last several years. The SiC community has recognized that the root cause of Vf drift in bipolar SiC devices is the expansion of basal plane dislocations (BPDs) into Shockley Stacking Faults (SFs) within device regions that experience conductivity modulation. In this presentation, we detail relatively simple procedures that reduce the density of Vf drift inducing BPDs in epilayers to <10 cm-2 and permit the fabrication of bipolar SiC devices with very good Vf stability. The first low BPD technique employs a selective etch of the substrate prior to epilayer growth to create a near on-axis surface where BPDs intersect the substrate surface. The second low BPD technique employs lithographic and dry etch patterning of the substrate prior to epilayer growth. Both processes impede the propagation of BPDs into epilayers by preferentially converting BPDs into threading edge dislocations (TEDs) during the initial stages of epilayer growth. With these techniques, we routinely achieve Vf stability yields of up to 90% in devices with active areas from 0.006 to 1 cm2, implying that the utility of the processes is not limited by device size.

Structure of the carrot defect in 4H-SiC epitaxial layers

Transmission electron microscopy and KOH etching were used to determine the structure of the carrot defect in 4H-SiC epilayers. The defect consists of two intersecting planar faults on prismatic {11¯00} and basal {0001} planes. Both faults are connected by a stair-rod dislocation with Burgers vector 1∕n [101¯0] with n>3 at the crossover. A Frank-partial dislocation with b=1∕12[44¯03] terminates the basal fault.

Glide and multiplication of basal plane dislocations during 4H‐SiC homoepitaxy

Basal plane dislocations (BPDs) are an important category of extended defects in SiC epilayers. They act as nucleation sites for single layer Shockley-type stacking faults which account for the degradation of the bipolar devices operating under forward bias. It is well documented that most of the BPDs in the SiC epilayers propagate from the substrates. However, two characteristic types of BPDs were suggested to be due to either nucleation or multiplication during epitaxy, including interfacial dislocations and short BPD arrays connected to the epilayer surface by threading segments. Combining molten KOH etching, plan-view transmission x-ray topography, and photoluminescence mapping, both types are determined to be two parts of one defect produced by the sideway glide of a BPD under the influence of shear stress. During the glide, the down-step end of the BPD frequently produces a series of short BPD segments at the moving growth front. These BPD segments will grow into an array of dislocation half loops. ...

100 mm 4HN-SiC Wafers with Zero Micropipe Density

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

Development of Large Area (up to 1.5 cm2) 4H-SiC 10 kV Junction Barrier Schottky Rectifiers

DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.

Approaches to Stabilizing the Forward Voltage of Bipolar SiC Devices

We identify several promising approaches to PiN diode fabrication, which greatly reduce forward voltage (Vf) drift in PiN diodes fabricated on standard 8° off-axis 4H-SiC substrates. Our best results require thick buffer layers and growing the entirety of the active device structure without interruption. We address the roles of buffer and drift layer thickness, continuous growth, processing variations and alternative substrate preparation, including ) 0 2 11 ( substrates, on Vf drift. Lastly we report on progress made to reduce the density of stacking fault nucleation sites in PiN diodes.

Morphology of basal plane dislocations in 4H-SiC homoepitaxial layers grown by chemical vapor deposition

The morphology of basal plane dislocations (BPDs) in 4H-SiC homoepitaxial layers has been investigated by plan-view transmission x-ray topography and molten KOH etching. Three types of BPDs are distinguished based on their morphologies. These include interfacial dislocations, curved dislocations, and circular loop dislocations around micropipes. Their characteristics are studied in detail and possible sources of their formation during epitaxy are discussed.

High Power 4H-SiC PiN Diodes with Minimal Forward Voltage Drift

Abstract. Rapid advancement has been shown for 4H-SiC PiN diodes. High quality epitaxial drift layers as thick as 200 μm (17.3 kV breakdown voltage) have been grown for PiN structures having a forward voltage drop (VF, at 100 A/cm 2 ) as low as 6.3 V for 3 mm diameter devices. As impressive as these results are, 4H-SiC PiN diodes continue to suffer from forward voltage instability. Recently, great strides have been made in 4H-SiC epitaxy to produce relatively driftfree PiN structures. Large area power devices capable of handling up to 7.5 A of current and blocking 10 kV have been fabricated on this state of the art epitaxy. To maximize the breakdown voltage, a three zone Junction Termination Extension (JTE) was formed via boron ion implantation. Low resistance (~10 -7 Ω-cm 2 ) contacts to p-type 4H-SiC, high carrier lifetime (~1 μsec) and improved injection efficiency of the epitaxial material enable a record low VF of 3.74 V on a 100 μm drift layer. More importantly, 20% of the yielded large area parts (0.05 cm 2 and 0.075 cm 2 ) exhibit a high degree of forward voltage stability.

Large Area SiC Epitaxial Layer Growth in a Warm-Wall Planetary VPE Reactor

Experimental results are presented for SiC epitaxial layer growths employing a largearea, 7x3-inch, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 30-micron thick, specular, device-quality SiC epitaxial layers with background doping concentrations of <1x1014 cm-3. Multi-layer device profiles such as Schottky, MESFETs, SITs, and BJTs with n-type doping from ~1x1015 cm-3 to >1x1019 cm-3, p-type doping from ~3x1015 cm-3 to >1x1020 cm-3, and abrupt doping transitions (~1 decade/nm) are regularly grown in continuous growth runs. Intrawafer layer thickness and n-type doping uniformities of <1% and <5% s/mean have been achieved. Within a run, wafer-to-wafer thickness and doping variation are ~±1% and ~±5% respectively. Long term run-to-run variations while under process control are approximately ~3% s/mean for thickness and ~5% s/mean for doping. Latest results from an even larger 6x4-inch (100-mm) reactor are also presented.

Defect Status in SiC Manufacturing

Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMP) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.