R.T. Leonard

Sublimation-Grown Semi-Insulating SiC for High Frequency Devices

In this paper we show the progression in the development of semi-insula ti g SiC grown by the sublimation technique from extrinsically doped material to hig h purity semi-insulating (HPSI) 4H-SiC bulk crystals of 2-inch and 3-inch diameter without re sorting to the intentional introduction of elemental deep level dopants, such as vanadium. Secondary ion m ass spectrometry, optical absorption, deep level transient spectroscopy and electron parama gnetic resonance data suggest that the semi-insulating behavior in HPSI material orig inates from deep levels associated with intrinsic point defects. While high temperature resistivity measurements on different high purity 4H-SiC samples indicate activation energies ranging from 0.9 to 1.6 eV, HPSI wafers with homogeneous activation energies near mid-gap are demonstrated. The roomtemperature thermal conductivity of this material approaches the theoretical maximum of ~ 5 W/cmK. Additionally, HPSI substrates exhibit micropipe densities as low as 8 cm -2 over the full diameter of a 3-inch wafer. MESFETs produced on HPSI wafers are free of backgating effects and have resulted in the best combination of power density and efficiency reported to date for SiC M ESFETs of 5.2 W/mm and 63% power added efficiency (PAE) at 3.5 GHz.

100 mm 4HN-SiC Wafers with Zero Micropipe Density

Recent advances in PVT c-axis growth process have shown a path for eliminating micropipes in 4HN-SiC, leading to the demonstration of zero micropipe density 100 mm 4HN-SiC wafers. Combined techniques of KOH etching and cross-polarizer inspections were used to confirm the absence of micropipes. Crystal growth studies for 3-inch material with similar processes have demonstrated a 1c screw dislocation median density of 175 cm-2, compared to typical densities of 2x103 to 4x103 cm-2 in current production wafers. These values were obtained through optical scanning analyzer methods and verified by x-ray topography.

Silicon Carbide Crystal and Substrate Technology: A Survey of Recent Advances

The quest of driving SiC toward the realization of its full potential as a semiconductor material continues in many organizations world-wide. R&D and manufacturing efforts continue to address issues of scale-up of wafer size, improvements in wafer shape and surface characteristics, reduction of background impurities in bulk crystals, controlled uniformity of electrical properties, and reduction and control of crystalline defects. Significant progress has been made in several key areas. Increased manufacturing activity in the production of 3-inch diameter crystals has led to substrates with micropipes densities <30 cm -2 in n-type and <80 cm -2 in semi-insulating material, and R&D demonstrations of substrates exhibiting micropipe densities <0.5 cm -2 in n-type and <5 cm -2 in semi-insulating wafers. Developmental 100-mm diameter substrates exhibiting micropipe densities <60 cm -2 in both n-type and semi-insulating materials have now been demonstrated. Significant improvement in bulk crystal purity has been achieved with reduction of impurity concentrations below 5 x 10 15 cm -3 .

Large Diameter 4H-SiC Substrates for Commercial Power Applications

The SiC power device market is predicted to grow exponentially in the next few years. In the development of substrates for this emerging commercial market, it is imperative to develop the product to meet the needs of the targeted application. In this paper we will discuss the status and requirements for SiC substrates for power devices such as Schottky and PiN diodes. For example, for the SiC Schottky device where current production is approaching 50 amp devices, there are several substrate material aspects that are key. These include: wafer diameter (3-inch and 100 mm), micropipe density (<1cm -2 for 3-inch substrates and as low as 30cm -2 for 100-mm substrates), dislocation density, and wafer cost.

Defect Status in SiC Manufacturing

Availability of high-quality, large diameter SiC wafers in quantity has bolstered the commercial application of and interest in both SiC- and nitride-based device technologies. Successful development of SiC devices requires low defect densities, which have been achieved only through significant advances in substrate and epitaxial layer quality. Cree has established viable materials technologies to attain these qualities on production wafers and further developments are imminent. Zero micropipe (ZMPuf0d4) 100 mm 4HN-SiC substrates are commercially available and 1c dislocations densities were reduced to values as low as 175 cm-2. On these low defect substrates we have achieved repeatable production of thick epitaxial layers with defect densities of less than 1 cm-2 and as low as 0.2 cm-2. These accomplishments rely on precise monitoring of both material and manufacturing induced defects. Selective etch techniques and an optical surface analyzer is used to inspect these defects on our wafers. Results were verified by optical microscopy and x-ray topography.

Status of 4H-SiC Substrate and Epitaxial Materials for Commercial Power Applications

The performance enhancements offered by the next generation of SiC high power devices offer potential for enormous growth in SiC power device markets in the next few years. For this growth to occur, it is imperative that substrate and epitaxial material quality increases to meet the needs of the targeted applications. We will discuss the status and requirements for SiC substrates and epitaxial material for power devices such as Schottky and PiN diodes. For the SiC Schottky device where current production is approaching 50 amp devices, there are several material aspects that are key. These include; wafer diameter (3-inch and 100-mm), micropipe density ( −2 for 3-inch substrates and 16 cm −2 for 100-mm substrates), epitaxial defect densities (total electrically active defects −2 ), epitaxial doping and epitaxial thickness uniformity. For the PiN diodes the major challenge is the degradation of the Vf characteristics due to the introduction of stacking faults during the device operation. We have demonstrated that the stacking faults are often generated from basal plane dislocations in the active region of the device. Additionally we have demonstrated that by reducing the basal plane dislocation density, stable PiN diodes can be produced. At present typical basal plane dislocation densities in our epitaxial layers are 100 to 500 cm −2 ; however, we have achieved basal plane dislocation densities as low as 4 cm −2 in epitaxial layers grown on 8° off-axis 4H-SiC substrates.

Bulk Growth of Large Area SiC Crystals

The growth of large diameter silicon carbide (SiC) crystals produced by the physical vapor transport (PVT) method is outlined. Methods to increase the crystal diameters, and to turn these large diameter crystals into substrates that are ready for the epitaxial growth of SiC or other non homogeneous epitaxial layers are discussed. We review the present status of 150 mm and 200 mm substrate quality at Cree, Inc. in terms of crystallinity, dislocation density as well as the final substrate surface quality.

SiC Epitaxial Growth on Multiple 100-mm Wafers and its Application to Power-Switching Devices

The development of SiC bulk and epitaxial materials is reviewed with an emphasis on epitaxial growth using high-throughput, multi-wafer, vapor phase epitaxial (VPE) warm-wall planetary reactors. It will be shown how the recent emergence of low-cost high-quality 100-mm diameter epitaxial SiC wafers is enabling the economical production of advanced wide-bandgap Power–Switching devices.

SiC warm-wall planetary VPE growth on multiple 100-mm diameter wafers

Experimental results are presented for SiC epitaxial layer growth employing a large-area, up to 8x100-mm, warm-wall planetary SiC-VPE reactor. This high-throughput reactor has been optimized for the growth of uniform 0.01 to 80-micron thick, specular, device-quality SiC epitaxial layers with low background doping concentrations of <1x1014 cm-3 and intentional p- and n-type doping from ~1x1015 cm-3 to >1x1019 cm-3. Intrawafer layer thickness and n-type doping uniformity (σ/mean) of ~2% and ~8% have been achieved to date in the 8x100-mm configuration. The total range of the average intrawafer thickness and doping within a run are approximately ±1% and ±6% respectively.

Reliability assessment of a large population of 3.3 kV, 45 A 4H-SIC MOSFETs

In this work, we report results for the 3 lot, 77 device-per-lot high temperature-reverse bias (HTRB) test, as well as work on gate oxide reliability for 3.3 kV devices in relation to the presence of material defects. The work indicates that large scale reliable operation of 3.3 kV 4H-SIC MOSFETs is achievable using conventional 4H-SiC device processing techniques and DMOS device structures, despite the prevalence of measurable surface morphology on 3.3 kV SiC epilayers. No correlation was found between dislocation content and MOS capacitor breakdown field, measured on over 14 cm2 of combined tested 4H-SIC MOS gate area.