Michael L. Bushnell

Delay fault models and test generation for random logic sequential circuits

The authors study the problem of delay fault modeling and test generation for any random logic sequential circuit. The proposed test generation method, based on transition and hazard states of signals, is applicable to any sequential circuit of either non-scan, scan or scan-hold type of design. Three fault models based on different initial state assumptions during the propagation of the fault effect to a primary output are proposed and analyzed using the proposed delay fault test generation method. A novel thirteen-value algebra is considered to simplify the analysis of robust and nonrobust tests during fault simulation of path delay faults.<<ETX>>

Path delay fault simulation of sequential circuits

To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transition conditions for two consecutive vectors. After the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flip-flop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The simulation is independent of the specific delays of the combinational elements, and either robust or nonrobust detection can be simulated as options to the user. For robust simulation, an update rule for state variables is proposed whereby a flip-flop is updated with its correct value, provided it is a destination of at least one robustly activated path. This rule gives a higher and more realistic coverage of robustly detected faults. Experimental results verify the effectiveness of the simulator. >

Toward massively parallel automatic test generation

A new automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. This approach is radically different from the conventional methods used to generate tests for circuits from their gate level description. The digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. The authors simulated the neural network on a serial computer, and determined the global minima of the energy function using a directed search technique augmented by probabilistic relaxation. Preliminary results on combinational circuits confirm the feasibility of this technique. >

Digital circuit design for minimum transient energy and a linear programming method

This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. The theory in this paper allows trade-offs between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay buffers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53% peak and 73% average power compared to the original circuit.

Neural models and algorithms for digital testing

1 Introduction.- 1.1 What is Test Generation?.- 1.2 Why Worry About Test Generation?.- 1.3 How About Parallel Processing?.- 1.4 Neural Computing.- 1.5 A Novel Solution.- 1.6 Polynomial Time Test Problems.- 1.7 Application to Other NP-complete Problems.- 1.8 Organization of the Book.- References.- 2 Logic Circuits and Testing.- 2.1 Logic Circuit Preliminaries.- 2.2 Test Generation Problem.- 2.2.1 FaultModeling.- 2.2.2 Problem Definition.- 2.2.3 Complexity of Test Generation.- 2.3 Test Generation Techniques.- 2.4 Parallelization.- References.- 3 Parallel Processing Preliminaries.- 3.1 Synchronous Parallel Computing.- 3.1.1 Program Representation.- 3.1.2 Identification of Program Parallelism.- 3.1.3 Partitioning and Scheduling.- 3.1.4 Performance Measures.- 3.1.5 Solving Problems Using Multiprocessors.- 3.2 Parallel Test Generation.- References.- 4 Introduction to Neural Networks.- 4.1 Discrete Model of Neuron.- 4.2 Electrical Neural Networks.- References.- 5 Neural Modeling for Digital Circuits.- 5.1 Logic Circuit Model.- 5.2 Existence of Neural Models.- 5.2.1 Neural Networks in Basis Set are Optimal.- 5.2.2 Parameters of Energy Function.- 5.3 Properties of Neural Models.- 5.4 Three-Valued Model.- 5.5 Summary.- References.- 6 Test Generation Reformulated.- 6.1 ATG Constraint Network.- 6.2 Fault Injection.- 6.3 Test Generation.- 6.4 Summary.- References.- 7 Simulated Neural Networks.- 7.1 Iterative Relaxation.- 7.2 Implementation and Results.- 7.2.1 Test Generation System.- 7.2.2 Experimental Results.- 7.3 Parallel Simulation.- 7.3.1 Synchronous Parallelism..- 7.3.2 Asynchronous Parallelism.- 7.4 Summary.- References.- 8 Neural Computers.- 8.1 Feasibility and Performance.- 8.2 ANZA Neurocomputer.- 8.3 Energy Minimization.- 8.4 Enhanced Formulation.- 8.4.1 Transitive Closure.- 8.4.2 Path Sensitization.- 8.5 ANZA Neurocomputer Results.- 8.6 Summary.- References.- 9 Quadratic 0-1 Programming.- 9.1 Energy Minimization.- 9.2 Notation and Terminology.- 9.3 Minimization Technique.- 9.4 AnExample.- 9.5 Accelerated Eneigy Minimization.- 9.5.1 Transitive Closure.- 9.5.2 Additional Pairwise Relationships.- 9.5.3 Path Sensitization.- 9.6 Experimental Results.- 9.7 Summary.- References.- 10 Transitive Closure and Testing.- 10.1 Background.- 10.2 Transitive Closure Definition.- 10.3 Implication Graphs.- 10.4 A Test Generation Algorithm.- 10.5 Identifying Necessary Assignments.- 10.5.1 Implicit Implication and Justification.- 10.5.2 Transitive Closure Does More Than Implication and Justification.- 10.5.3 Implicit Sensitization of Dominators.- 10.5.4 Redundancy Identification.- 10.6 Summary.- References.- 11 Polynomial-time Testability.- 11.1 Background.- 11.1.1 Fujiwaras Result.- 11.1.2 Contribution of the Present Work.- 11.2 Notation and Terminology.- 11.3 A Polynomial Time Algorithm.- 11.3.1 Primary Output Fault.- 11.3.2 Arbitrary Single Fault.- 11.3.3 Multiple Faults.- 11.4 Summary.- References.- 12 Special Cases of Hard Problems.- 12.1 Problem Statement.- 12.2 Logic Simulation.- 12.3 Logic Circuit Modeling.- 12.3.1 Model for a Boolean Gate.- 12.3.2 Circuit Modeling.- 12.4 Simulation as a Quadratic 0-1 Program.- 12.5 Quadratic 0-1 Program as Simulation.- 12.5.1 A Linear Time Algorithm.- 12.6 Minimizing Special Cases.- 12.7 Summary.- References.- 13 Solving Graph Problems.- 13.1 Background.- 13.2 Notation and Terminology.- 13.3 Maximum Weighted Independent Sets.- 13.4 Conflict Graphs of Boolean Gates.- 13.5 AnExample.- 13.6 Summary.- References.- 14 Open Problems.- References.- 15 Conclusion.

Classification and Test Generation for Path-Delay FaultsUsing Single Struck-at Fault Tests

We classify all path-delay faults of a combinational circuit intothree categories: singly-testable (ST), multiply-testable (MT), and singly-testable dependent} (ST-dependent). The classification uses anyunaltered single stuck-at fault test generation tool. Only two runsof this tool on a model network derived from the original network areperformed. As a by-product of this process, we generate single andmultiple input change delay tests for all testable faults. With thesetests, we expect that most defective circuits are identified. All STfaults are guaranteed detection in the case of a single fault, andsome may be guaranteed detection through robust and validatablenon-robust tests even in the case of multiple faults. An ST-dependentfault can affect the circuit speed only if certain ST faults arepresent. Thus, if all ST faults are tested, the ST-dependent faultsneed not be tested. MT faults cannot be guaranteed detection, butaffect the speed only if delay faults simultaneously exist on a setof paths, none of which is ST. Examples and results on several ISCAS‘89 benchmarks are presented. The method of classification throughtest generation using a model network is complex and can be appliedto circuits of moderate size. For larger circuits, alternativemethods will have to be explored in the future.

Test generation for mixed-signal devices using signal flow graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.

The path-status graph with application to delay fault simulation

We present an efficient path-delay fault (PDF) simulator that does not involve the enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the path-status graph (PSG), to efficiently hold the status of each PDF in the circuit, i.e., whether or not the PDF is tested. The keg to this efficiency is in breaking the information into pieces and distributing it over the data structure, and in retaining all or part of the reconverging fan-out structure of the circuit in the PSG. Thus, an exponential number of PDFs can share the same piece of information. Using 1000 random tests, we simulated all of the approximately 10/sup 20/ PDFs in the circuit c6288, and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods.

Variable input delay CMOS logic for low power design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

A tutorial on the emerging nanotechnology devices

This paper provides an overview of the research on nanometer scale electronic switching devices. Such devices are likely to be used for building ultra-density integrated electronic computers of the future. We first describe the problems faced by the downscaling of FET devices and then discuss the emerging alternatives: 1) Carbon Nanotube transistors 2) Quantum effect and single-electron devices and 3) Molecular electronic devices. We discuss the basic operating principle of each type of device. Here mathematical details have been suppressed in favor of simpler understanding. The present state of the art for each new device is given, outlining the open problems for research. Finally, a possible time-line for their large-scale implementation is given.