Tezaswi Raja

Variable input delay CMOS logic for low power design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

A tutorial on the emerging nanotechnology devices

This paper provides an overview of the research on nanometer scale electronic switching devices. Such devices are likely to be used for building ultra-density integrated electronic computers of the future. We first describe the problems faced by the downscaling of FET devices and then discuss the emerging alternatives: 1) Carbon Nanotube transistors 2) Quantum effect and single-electron devices and 3) Molecular electronic devices. We discuss the basic operating principle of each type of device. Here mathematical details have been suppressed in favor of simpler understanding. The present state of the art for each new device is given, outlining the open problems for research. Finally, a possible time-line for their large-scale implementation is given.

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.

CMOS circuit design for minimum dynamic power and highest speed

A new low-power design method produces CMOS circuits that consume the least dynamic power at the highest speed permitted under the technology constraint. A gate is characterized by an inertial delay and separate delays between its inputs and output. The technology constraint, related to feasible ranges of lengths and widths of transistors, is specified by a parameter u/sub b/. It is the upper bound on the difference between the input to output delays corresponding to any pair of inputs of a gate. We formulate a linear program (LP) whose size is proportional to the circuit size. This LP determines the inertial delay as well as input to output delays for each gate of the circuit with the given u/sub b/, such that all glitches are eliminated and the overall delay of the circuit is minimized. Because of the additional flexibility in specifying gate delays, the glitch suppression is guaranteed without any delay buffers. Hence this design consumes less power than those designed by other methods. We designed the circuit c1355 with 46% of the original power dissipation compared to a reference design. A previously published method, that characterizes each gate with a single delay, produced a c1355 circuit consuming 58% of the original power. Both low-power circuits had the same overall delay. The previous design required 224 delay buffers, whereas the new design needed none.

Transistor Sizing of Logic Gates to Maximize Input Delay Variability

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay (VID) gate and the maximum difference in delays of any two paths through the gate is known as “ub.” The VID gates have a known application in minimizing the active power of a digital CMOS circuit. A previous publication has proposed three different designs for implementing VID gates. In this paper, we describe transistor sizing methods to implement the three types of VID gates for any specified delay requirement. We also describe techniques for calculating the ub for each type of gate design. We outline an algorithm for an efficient determination of the transistor sizes for a gate for given delays and output load capacitance. The algorithm is a two-step approach with a look-up table of sizes in the first stage and a sensitivity based steepest descent method for the second stage. We also give a brief introduction to the power saving potential by maximizing ub when used in conjunction with the previously published technique.

Design of variable input delay gates for low dynamic power circuits

The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed to have the same input to output delay irrespective of which input caused the output to change. A gate which can offer different delays for different input-output paths through it, is known as a variable input delay(VID) gate and the maximum difference in delay between any two paths through the same gate is known as “ub”. These gates can be used for minimizing the active power of a digital CMOS circuit using a previosuly described technique called variable input delay(VID) logic. This previous publication proposed three different designs for implementating the VID gate. In this paper, we describe a technique for transistor sizing of these three flavors of the VID gate for a given delay requirement. We also describe techniques for calculating the ub of each flavor. We outline an algorithm for quick determination of the transistor sizes for a gate for a given load capacitance.

An Energy-Recovering Reconfigurable Series Resonant Clocking Scheme for Wide Frequency Operation

On-chip low skew clock distribution driving large load capacitances can consume as much as 70% of the total dynamic power that is lost as heat, resulting in high cooling costs. To mitigate this, an energy recovering reconfigurable series resonance solution with all the critical support circuitry is described. This LC resonant clock driver on a 22 nm process node saves about 50% driver power ( >40% overall) and has 50% less skew than non-resonant driver at 2 GHz, while operating down to 0.2 GHz for dynamic voltage and frequency scaling. Reconfiguring for pulse mode operation enables further power saving, using latches instead of flip-flop banks, for double data rate applications. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared and verified, to enable synthesis of an optimal topology for a given application.

Modeling and measurement of noise aware clocking in power supply noise analysis

Power noise aware clocking in modern chips can reduce power supply noises and relax on-chip timing requirements during power drooping. This paper proposes and demonstrates a power noise simulation method to consider these two effects. Measurement results are also presented.

Using a Jini based desktop Grid for test vector compaction and a refined economic model

Testing of very large scale integrated (VLSI) circuits is done by designing huge random sets of vectors of which only a few are useful. The process of filtering these good vectors from the overall set is called vector compaction. As the integrated circuits become denser, this problem is becoming a major bottleneck and the computation time could run into days for a single chip. In this paper we demonstrate how a distributed Grid architecture can be used for the speed-up of the problem. The architecture is based on a Jini desktop Grid. Economic models become a prime issue in such a scenario. The current economic models for minimizing cost or time are ad-hoc and entirely under the control of the broker middleware architecture, leaving the end user with little choice. In this paper we present a revised economic model that gives more choice to the user in terms of time and cost before execution. We match the high-level application layer to the available resources by utilizing a system of composite performance modeling of the available resources. We demonstrate the performance of this new architecture on some VLSI benchmark circuits.