Michael Markert

A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control

A 2-Mbit CBRAM (Conductive Bridging Random Access Memory) core has been developed utilizing a 90 nm, VDD=1.5 V process technology. The presented design uses an 8F2 (0.0648 mum2) 1T1CBJ (1-Transistor/1-Conductive Bridging Junction) cell and introduces a fast feedback regulated CBJ read voltage and a novel program charge control using dummy cell bleeder devices. Random read/write cycle times les50ns are demonstrated

Time Discrete Voltage Sensing and Iterative Programming Control for a 4F 2 Multilevel CBRAM

Multilevel read/write circuits developed for a 90 nm, 4F2, 1T1CBJ (1-transistor/1-conductive bridging junction) 4Mb CBRAM core are described for the first time. The design uses an on-pitch time-discrete voltage sensing scheme and employs a bitline (BL) charge balancing reference as well as a self-timed iterative program concept. Random read cycle times ap0.7 mus and random write cycle times ap1.35 mus are achieved.