Michael S. Gordon

Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground

New ground-based measurements of the cosmic-ray induced neutron flux and its energy distribution have been made at several locations across the United States using an extended-energy Bonner sphere spectrometer. The data cover over twelve decades of neutron energy, from meV to GeV. An expression to scale the flux to other locations has been developed from a fit to the altitude dependence of our measurements and an expression from the literature for the geomagnetic and solar-activity dependence of neutron monitor rates. In addition, an analytic expression is provided which fits the neutron spectrum above about 0.4 MeV. The neutron flux is important for estimating the soft-error rate in computer memories and recent computer logic devices.

SRAM SER in 90, 130 and 180 nm bulk and SOI technologies

We investigate the soft error rate (SER) of bulk and SOI SRAMs at the 90, 130 and 180 nm technology nodes. We use accelerated testing and Monte Carlo modeling to determine SER sensitivity to different radiation sources; we can therefore predict the product SER based on the radiation flux. Lifetests performed underground, near sea level, and at 10,000 feet confirm the predicted SER levels.

Projection reduction exposure with variable axis immersion lenses: Next generation lithography

Projection reduction exposure with variable axis immersion lenses (PREVAIL) represents the high throughput e-beam projection approach to NGL, which IBM is pursuing in cooperation with Nikon as alliance partner; another e-beam projection approach is SCALPEL pursued by Lucent Technologies. This article discusses the challenges and accomplishments of the PREVAIL project. It will focus on the results obtained with the proof of concept (POC) system. This system was developed to demonstrate key technical building blocks required for high throughput, high resolution e-beam step, and scan projection lithography. The supreme challenge facing all e-beam lithography approaches has been and still is throughput. Since the throughput of e-beam projection systems is severely limited by the available optical field size, the key to success is the ability to overcome this limitation. The PREVAIL technique overcomes field-limiting off-axis aberrations through the use of variable axis lenses, which electronically shift the o...

Alpha-particle-induced upsets in advanced CMOS circuits and technology

In this paper, we review the current status of single-event upsets caused by alpha-particles in IBM circuits and technology. While both alpha-particles and cosmic radiation can induce upsets, the alpha-particle-induced upset rate has become an increasingly important issue because alpha-particle-induced upsets are no longer limited to memory circuits. Latch circuits have become highly sensitive to alpha-particles. The alpha-particle-induced upset rate of latch circuits is one of the most critical issues for microprocessors requiring both high performance and high reliability.

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

EL‐4, a new generation electron‐beam lithography system

The new generation electron‐beam lithography system EL‐4 is described, designed for direct wafer exposure as well as optical reticle and x‐ray mask making. The new architecture features control through workstations and local area network communication between these and the microprocessor‐controlled subsystems. The system has on‐line error checking and diagnostics. Wafers up to 200 mm diam are handled individually with a Standard Mechanical InterFace‐compatible, fully robotic system, and are electrostatically chucked to the stage. Reticles are clamped to the stage with double‐sided e/s chucks, ring‐bonded membrane masks are kinematically held in a carrier chucked to the stage. The reticle/mask maker has an internal temperature control system in addition to the clean‐room climate control for the entire mechanical hardware. The electron optics accommodate triangle as well as rectangle spot formation, and for direct write application a throughput‐enhancing third level in the deflection hierarchy. High resolut...

An Evaluation of An Ultralow Background Alpha-Particle Detector

XIA has provided IBM with a prototype ultralow background alpha particle counter for evaluation. Results show a significant decrease in background compared to other commercial counters allowing for rapid measurement of low-emissivity materials.

Single-event-upset and alpha-particle emission rate measurement techniques

The susceptibility of modern integrated-circuit devices to single-event upsets (SEUs) depends on both the alpha-particle emission rate and the energy of the alpha-particles emitted. In addition, the terrestrial neutron energy and flux, which produce secondary charged fragments in the device and circuit at the location of operation, contribute to the SEU rate. In this paper, we discuss methods that are used to measure alpha-particle emissivity from semiconductor and packaging materials, as well as methods that we used and our results for life testing and accelerated SEU testing of modern devices.

Technologies to further reduce soft error susceptibility in SOI

Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements. Our methodology is first introduced, and the following techniques are examined in detail: 1) Body thinning, 2) carrier lifetime reduction, 3) body contacts, 4) stacked devices, and 5) parallel devices. Finally, the advantages and disadvantages of all methods are described.