Henry H. K. Tang

Accurate, predictive modeling of soft error rate due to cosmic rays and chip alpha radiation

We report here the development of a unique and comprehensive computer program (SEMM) to calculate the probability of soft fails in integrated circuits due to alpha particles emanating from the chip materials and due to terrestrial cosmic rays. This model treats all failure modes on an event by event basis allowing for all nuclear reactions and pulse shape effects. It is a three-dimensional design tool that takes the detailed chip layout and profile information to compute the soft error rate and is used without any parameter fitting. SEMM has been extensively tested with hot sources, high energy proton beams, and high elevation cosmic ray tests. Applications of SEMM to bipolar and CMOS chips and considerations for building in reliability for radiation induced soft fails are also discussed.<<ETX>>

SEMM-2: a modeling system for single event upset analysis

We describe SEMM-2, a new simulation system for the analysis of radiation-induced single event upsets which builds on the initial SEMM tool. Developed for the current and future CMOS technologies, SEMM-2 improves the generation of radiation events. The atomic databases which describe ion energy loss with transport through device materials are generalized. Enhancements of the nuclear collision event generation include more accurate and efficient methods for generating elastic events and more thorough treatment of inelastic processes. We present illustrative simulations where more accurately accounting for the metallization layers significantly impacts the simulated single event failure rate.

Parameter-free, predictive modeling of single event upsets due to protons, neutrons, and pions in terrestrial cosmic rays

In this paper we present a new approach and a computer software for modeling single event upsets. This model, named Soft Error Monte Carlo Model (SEMM), does not need any experimental inputs or any parameter fitting. It is intended to be a design tool for chip designers when they want to optimize their designs for soft error hardness and performance. The paper focuses on terrestrial cosmic rays that cause single event upsets. Details of the nuclear modeling and of the coupled device-circuit modeling are presented. Also presented are the comparison of SEMM predictions against measurements of single event upset rate in proton beam experiments and in computer main frame field tests performed at high ground elevations. We also present some proton-pion comparisons that are relevant to single event upsets. >

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

Technologies to further reduce soft error susceptibility in SOI

Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements. Our methodology is first introduced, and the following techniques are examined in detail: 1) Body thinning, 2) carrier lifetime reduction, 3) body contacts, 4) stacked devices, and 5) parallel devices. Finally, the advantages and disadvantages of all methods are described.

Importance of BEOL Modeling in Single Event Effect Analysis

Novel techniques have been developed to simulate particle transport in arbitrarily complex back-end-of-line topologies. They are shown to be critical for single event effect analyses of new device structures for 65 nm CMOS technologies and beyond. The salient features of the new modeling methods are illustrated by the simulation results taken from several case studies of particle-induced radiation problems in the back end.

Multi-bit upsets in 65nm SOI SRAMs

We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.

Air spacer for 10nm FinFET CMOS and beyond

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15–25% reduction in overlap capacitance (COT)) and at ring oscillator level (10–15% reduction in effective capacitance (Cf)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

Stacked devices for SEU immune design

A stacked transistor on SOI shows the potential to provide soft error upset immune designs. Key design elements are presented and analyzed showing tradeoffs between standard SOI devices and stacked devices, as well as alternative layouts to optimize soft error upset immunity.

Protecting Big Blue from Rogue Subatomic Particles

Device technology scaling continues to deliver faster and smaller transistors, contributing to IBMs continued leadership in server systems. However, there is also a dark side to device technology scaling. As transistors shrink, the amount of charge required to change the logic state of a memory or a logic circuit (i.e. flip a 1 to a 0 and vice versa) also shrinks. This complication spurs continued effort at IBM to test, characterize, and mitigate these transient bit flips, so called soft errors. In this paper we survey our ongoing work in this realm and introduce our views on trends for soft errors in future device technologies.