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Dive into the research topics where Michael S. Gray is active.

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Featured researches published by Michael S. Gray.


international solid-state circuits conference | 2008

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

Osamu Takahashi; Chad Adams; D. Ault; Erwin Behnen; O. Chiang; Scott R. Cottier; Paula Kristine Coulman; James A. Culp; Gilles Gervais; Michael S. Gray; Y. Itaka; C. J. Johnson; Fumihiro Kono; L. Maurice; Kevin W. McCullen; Lam M. Nguyen; Yoichi Nishino; Hiromi Noro; Jürgen Pille; Mack W. Riley; M. Shen; Chiaki Takano; Shunsako Tokito; Tina Wagner; Hiroshi Yoshihara

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.


international conference on computer aided design | 2007

Practical method for obtaining a feasible integer solution in hierarchical layout optimization

Xiaoping Tang; Xin Yuan; Michael S. Gray

Layout optimization is a powerful technique for design migration, circuit performance tuning and design for manufacturing. In this paper, we study the problem of layout optimization for the hierarchical circuits in modern VLSI designs which essentially can be formulated as the integer linear programming (ILP) problem. Existing approaches are either unable to handle hierarchy, inefficient or failing to provide the feasible integer solutions for large scale hierarchical layouts. We present a practical method, IRLS algorithm (iteratively rounding and LP solving) which consists of a proper rounding strategy based on the careful analysis of hierarchical layout constraints, to obtain a feasible integer solution in the constraint-based layout modification process, thus enabling efficient optimization for large scale hierarchical layouts, and specifically avoiding the need to use the general ILP solvers. Experimental results demonstrate the efficiency and effectiveness of the IRLS algorithm. Compared with the general ILP/MILP solver, the IRLS algorithm can obtain decent results with much less runtime (speed-up ranging from 4.000X to 360.000X). Compared with the two-step approach(Allen et al., 2003) on legalizing a set of large scale industry circuit layouts, the IRLS algorithm can provide much better solution (satisfying all abutment/alignment constraints that the two-step approach fails to meet).


Archive | 2006

MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CONSTRAINTS FOR HIERARCHICAL DESIGNS

Robert J. Allen; Michael S. Gray; Fook-Luen Heng; Jason D. Hibbeler; Kevin W. McCullen; Rani Narayan; Robert F. Walker; Xin Yuan


Archive | 1990

Stylus sensing system

Evon C. Greanias; Frank L. Stein; Robert L. Donaldson; Michael S. Gray


Archive | 1993

Stylus tilt detection apparatus for communication with a remote digitizing display

Karl David Schubert; Guy F. Verrier; Michael S. Gray


Archive | 2006

IC Layout Optimization to Improve Yield

Robert J. Allen; Faye D. Baker; Albert M. Chu; Michael S. Gray; Jason D. Hibbeler; Daniel N. Maynard; Mervyn Y. Tan; Robert F. Walker


Archive | 2004

INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS

Robert J. Allen; Michael S. Gray; Jason D. Hibbeler; Mervyn Y. Tan; Robert F. Walker


Archive | 2004

Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization

Michael S. Gray; Jason D. Hibbeler; Gustavo E. Tellez; Robert F. Walker


Archive | 2010

HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT

Michael S. Gray; Xiaoping Tang; Xin Yuan


Archive | 2007

OBTAINING A FEASIBLE INTEGER SOLUTION IN A HIERARCHICAL CIRCUIT LAYOUT OPTIMIZATION

Michael S. Gray; Xiaoping Tang; Xin Yuan

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