Kevin W. McCullen

Integrating DfM components into a cohesive design-to-silicon solution (Invited Paper)

Two primary tracks of DfM, one originating from physical design characterization, the other from low-k1 lithography, are described. Examples of specific DfM efforts are given and potentially conflicting layout optimization goals are pointed out. The need for an integrated DfM solution than ties together currently parallel DfM efforts of increasing sophistication and layout impact is identified and a novel DfM-enabling design flow is introduced.

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

Redundant Via Insertion in Restricted Topology Layouts

In this paper, the authors describe the application of redundant via insertion (RV) to the restricted topologies proposed for gridded and alternating phase shift mask layouts. Adding redundant vias has been shown to improve the yield and reliability of designs. The paper shows that it is possible to successfully add redundant vias, provided that the gridded layer is adjacent to a layer that can receive the additional layout complexity of the off-direction routing necessary to add additional vias. The authors compare a static method for via insertion that does not move existing wires with a dynamic method that shifts wires to make space for additional vias

Technology migration technique for designs with strong RET-driven layout restrictions

Restrictive design rules (RDRs) have been introduced as a simplified layout optimization method to better enable resolution enhancement techniques in ultra-deep submicron designs (16). In this paper, we study the technology migration problem for designs with strong RET-driven layout restrictions, i.e., RDR constraints, which require devices (gates) to be placed on a coarse pitch and in a single orientation. In particular, we study the legalization problem with on-pitch constraints for devices with an objective of minimum layout perturbation. The problem can be formulated as an integer linear programming (ILP) problem with a set of stringent integer constraints, and it can be approximated as a mixed integer linear programming (MILP) problem. Instead of using an MILP solver to solve it, we propose a two-stage method --- first the target on-pitch positions for gates are computed and second the original problem is relaxed to a linear programming problem. Library cell layouts designed in a technology with conventional ground rules have been migrated successfully to a technology with RDRs using our approach.