Michael Theobald

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams

An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented. OKFDDs are a generalization of OBDDs and OFDDs and as such provide a more compact representation of the functions than either of the two decision diagrams. In this paper basic properties of OKFDDs and their efficient representation and manipulation are presented. Based on the comparison of the three decision diagrams for several benchmark functions, a 25% improve ment in size over OBDDs is observed for OKFDDs.

MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines

Minimalist is a new extensible environment for the synthesis and veri cation of burst-mode asynchronous nite-state machines. Minimalist embodies a complete technology-independent synthesis path, with state-of-the-art exact and heuristic asynchronous synthesis algorithms, e.g. optimal state assignment (Chasm), two-level hazard-free logic minimization (Hfmin, Espresso-HF, and Impymin), and synthesis-for-testability. Unlike other asynchronous synthesis packages, Minimalist also o ers many options: literal vs. product optimization, singlevs. multi-output logic minimization, using vs. not using fed-back outputs as state variables, and exploring varied code lengths during state assignment, thus allowing the designer to explore trade-o s and select the implementation style which best suits the application. Minimalist benchmark results demonstrate its ability to produce implementations with an average of 34% and up to 48% less area, and an average of 11% and up to 37% better performance, than the best existing package [38]. Our synthesis-for-testability method guarantees 100% testability under both stuck-at and robust path delay fault models, requiring little or no overhead. Minimalist also features both command-line and graphic user interfaces, and supports extension via well-de ned interfaces for adding new tools. As such, it is easily augmented to form a complete path to technology-dependent logic.

Self-timed carry-lookahead adders

Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency which is /spl Theta/(nloglogn). An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively, and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.

Fast OFDD-based minimization of fixed polarity Reed-Muller expressions

We present methods to minimize fixed polarity Reed-Muller expressions (FPRMs), i.e., two-level fixed polarity AND/EXOR canonical representations of Boolean functions, using ordered functional decision diagrams (OFDDs). We investigate the close relation between both representations and use efficient algorithms on OFDDs for exact and heuristic minimization of FPRMs. In contrast to previously published methods, our algorithm can also handle circuits with several outputs. Experimental results on large benchmarks are given to show the efficiency of our approach.

Transformations for the synthesis and optimization of asynchronous distributed control

Asynchronous design has been the focus of renewed interest. However, a key bottleneck is the lack of high-quality CAD tools for the synthesis of large-scale systems which also allow design-space exploration. This paper proposes a new synthesis method to address this issue, based on transformations. The method starts with a scheduled and resource-bounded Control-Data Flow Graph (CDFG). Global transformations are first applied to the entire CDFG, unoptimized controllers are then extracted, and, finally, local transforms are applied to the individual controllers. The result is a highly-optimized set of interacting distributed controllers. The new transforms include aggressive timing- and area-oriented optimizations, several of which have not been previously supported by existing asynchronous CAD tools. As a case study the method is applied to the well-known differential equation solver synthesis benchmark. Results comparable to a highly-optimized manual design by Yun et al. (1997) can be obtained by applying the new automated transformations. Such an implementation cannot be obtained using existing asynchronous CAD tools.

Fast heuristic and exact algorithms for two-level hazard-free logic minimization

None of the available minimizers for two-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper introduces two new two-level hazard-free logic minimizers: ESPRESSO-HF, a heuristic method loosely based on ESPRESSO-II, and IMPYMIN, an exact method based on implicit data structures. Both minimizers can solve all currently available examples, which range up to 32 inputs and 33 outputs. These include examples that have never been solved before. For the more difficult examples that can be solved by other minimizers, our methods are several orders of magnitude faster. As by-products of these algorithms, we also present two additional results. First, we propose a fast new method to check if a hazard-free covering problem can feasibly be solved. Second, we introduce a novel reformulation of the two-level hazard-free logic minimization problem by capturing hazard-freedom constraints within a synchronous function through the addition of new variables.

Delay-insensitive carry-lookahead adders

Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.

Espresso-HF: a heuristic hazard-free minimizer for two-level logic

We present a new heuristic algorithm for hazard-free minimization of two-level logic. On nearly all examples, the algorithm finds an exactly minimum-cost cover. It also solves several problems which have not been previously solved using existing exact minimizers. We believe this is the first heuristic method based on Espresso to solve the general hazard-free two-level minimization problem, for multiple-input change transitions.

OKFDDs versus OBDDs and OFDDs

Ordered Decision Diagrams (ODDs) as a means for the representation of Boolean functions are used in many applications in CAD. Depending on the decomposition type, various classes of ODDs have been defined, the most important being the Ordered Binary Decision Diagrams (OBDDs), the Ordered Functional Decision Diagrams (OFDDs) and the Ordered Kronecker Functional Decision Diagrams (OKFDDs). In this paper we clarify the computational power of OKFDDs versus OBDDs and OFDDs from a (more) theoretical point of view. We prove several exponential gaps between specific types of ODDs. Combining these results it follows that a restriction of the OKFDD concept to subclasses, such as OBDDs and OFDDs as well, results in families of functions which lose their efficient representation.

On the Expressive Power of OKFDDs

Ordered Decision Diagrams (ODDs) as a means for the representation of Boolean functions are used in many applications in CAD. Depending on the decomposition type, various classes of ODDs have been defined, among them being the Ordered Binary Decision Diagrams (OBDDs), the Ordered Functional Decision Diagrams (OFDDs) and the Ordered Kronecker Functional Decision Diagrams (OKFDDs).Based on a formalization of the concept decomposition type we first investigate all possible decomposition types and prove that already OKFDDs, which result from the application of only three decomposition types, result in the most general class of ODDs. We then show from a (more) theoretical point of view that the generality of OKFDDs is really needed. We prove several exponential gaps between specific classes of ODDs, e.g. between OKFDDs on the one side and OBDDs, OFDDs on the other side. Combining these results it follows that a restriction of the OKFDD concept to subclasses, such as OBDDs and OFDDs as well, results in families of functions which lose their efficient representation.