Stephen H. Unger

GIT—a heuristic program for testing pairs of directed line graphs for isomorphism

Given a pair of directed line graphs, the problem of ascertaining whether or not they are isomorphic is one for which no efficient algorithmic solution is known. Since a straightforward enumerative algorithm might require 40 years of running time on a very high speed computer in order to compare two 15-node graphs, a more sophisticated approach seems called for. The situation is similar to that prevailing in areas such as game-playing and theorem-proving, where practical algorithms are unknown (for the interesting cases), but where various practical though only partially successful techniques are available. GIT—Graph Isomorphism Tester—incorporates a variety of processes that attempt to narrow down the search for an isomorphism, or to demonstrate that none exists. No one scheme is relied upon exclusively for a solution, and the program is designed to avoid excessive computation along fruitless lines. GIT has been written in the COMIT language and successfully tested on the IBM 7090.

Hazards and Delays in Asynchronous Sequential Switching Circuits

This paper is concerned with asynchronous, sequential switching circuits in which the variables are represented by voltage levels, not by pulses. The effects of arbitrarily located stray delays in such circuits are analyzed, and it is shown that, for a certain class of functions, proper operation can be assured regardless of the presence of stray delays and without the introduction of delay elements by the designer. All other functions require at least one delay element in their circuit realizations to insure against hazards. In the latter case it is shown that a single delay element is always sufficient. The price that must be paid for minimizing the number of delay elements is that of greater circuit complexity.

Hazards, critical races, and metastability

The various modes of failure of asynchronous sequential logic circuits due to timing problems are considered. These are hazards, critical races and metastable states. It is shown that there is a mechanism common to all forms of hazards and to metastable states. A similar mechanism, with added complications, is shown to characterize critical races. Means for defeating various types of hazards and critical races through the use of one-sided delay constraints are introduced. A method is described for determining from a flow table situations in which metastable states may be entered. A circuit technique is presented for extending a previously known technique for defeating metastability problems in self-timed systems. It is shown that the use of simulation for verifying the correctness of a circuit with given bounds on the branch delays cannot be relied upon to expose all timing problems. An example is presented that refutes a plausible conjecture that replacing pure delays with inertial delays can never introduce, but only eliminate glitches. >

Double-Edge-Triggered Flip-Flops

A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FFs behave in a complementary manner. Thus, these FFs can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FFs, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.

Self-timed carry-lookahead adders

Integer addition is one of the most important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency which is /spl Theta/(nloglogn). An economic implementation of this adder in CMOS technology is also presented. SPICE simulation results show that, based on random inputs, our 32-bit self-timed carry-lookahead adder is 2.39 and 1.42 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively, and, based on statistical data gathered from a 32-bit ARM simulator, it is 1.99 and 1.83 times faster than its synchronous counterpart and self-timed ripple-carry adder, respectively.

Asynchronous Sequential Switching Circuits with Unrestricted Input Changes

The problem of designing asynchronous circuits where the changes in binary input signals occur independently of one another is discussed. If several input changes occur within some interval δ1, the circuit behaves as though the changes were simultaneous. If consecutive changes are spaced by intervals exceeding some longer interval δ2 then the circuit reacts as though a sequence of single changes had occurred. But when the spacing is between these values, the system may react in an unsatisfactory manner unless special attention is paid to the problem during the design process. Constraints imposed by this problem on the row assignment and on the delay elements are derived.

A global parser for context-free phrase structure grammars

An algorithm for analyzing any context-free phrase structure grammar and for generating a program which can then parse any sentence in the language (or indicate that the given sentence is invalid) is described. The parser is of the “top-to-bottom” type and is recursive. A number of heuristic procedures whose purpose is to shorten the basic algorithm by quickly ascertaining that certain substrings of the input sentence cannot correspond to the target nonterminal symbols are included. Both the generating algorithm and the parser have been implemented in RCA SNOBOL and have been tested successfully on a number of artificial grammars and on a subset of ALGOL. A number of the routines for extracting data about a grammar, such as minimum lengths of N-derivable strings and possible prefixes, are given and may be of interest apart from their application in this particular context.

Flow Table Simplification-Some Useful Aids

Three results are presented pertinent to the problem of finding minimum-row versions of incompletely specified flow tables for sequential or iterative circuits. 1) Conditions are precisely stated under which preliminary mergers can be made without the danger of ruining opportunities for ultimately finding a minimal-row version. 2) A theorem by McCluskey is generalized to show that for all flow tables if optional entries arise only due to restrictions as to which input states may immediately follow one another, then the reduction problem is relatively simple. 3) A useful heuristic in the form of a diagram illustrating implication relations of 2-member compatibles is introduced as an aid in finding minimal closed sets of compatibles.

Delay-insensitive carry-lookahead adders

Integer addition is one of the mast important operations in digital computer systems because the performance of processors is significantly influenced by the speed of their adders. This paper proposes a delay insensitive, carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the logarithm of n. We also show an economic implementation of this adder in CMOS technology.

A Row Assignment for Delay-Free Realizations of Flow Tables Without Essential Hazards

Abstract—A method is presented for realizing any flow table that does not contain essential hazards with a circuit requiring no delay elements for proper operation. The procedure generally requires considerably fewer state variables than did an earlier technique for achieving the same result. It is based on a modification of a method by Tracey for constructing single-transition-time row assignments.