Michael Zelikson

A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor

This paper describes the second-generation Intel Core processor, a 32-nm monolithic die integrating four IA cores, a processor graphics, and a memory controller. Special attention is given to the circuit design challenges associated with this kind of integration. The paper describes the chip floor plan, the power delivery network, energy conservation techniques, the clock generation and distribution, the on-die thermal sensors, and a novel debug port.

Efficiency optimization of integrated DC-DC buck converters

An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. Microprocessors or chipsets exhibit wide dynamic range of load current varying from 50mA up to 1.5 A per phase at full operation. Peak efficiency is shown to occur when the load current related losses and the inherent losses of the DC-DC converter are equal. Efficiency optimization methods are described for light and heavy load scenarios. The primary design objective is to maintain the load at the peak of the efficiency curve. A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic methods.

4.1 14nm 6th-generation Core processor SoC with low power consumption and improved performance

Intels 6th generation Core processor (code named “Skylake” or SKL) was designed to enable PC performance and user-experience at smaller and thinner form factors and enable fan-less PC platforms. It required optimization to an extremely low thermal design point (TDP). The lower average power consumption of SKL vs. the previous generation considerably increases the system battery life and allows full-day battery life or thinner designs with smaller batteries. The SKL product family is manufactured using an Intel 14nm tri-gate CMOS 11-metal-layer technology, as with the previous Core generation. Different dice include: 2 or 4 cores, a shared last-level cache (LLC, 1MB/core), a scalable graphic processor (GP) with 24, 48 or 72 execution units (EU), an image processing unit (IPU, supporting 4 cameras simultaneously), 2 channels of DDR3/LPDDR3/DDR4, a display engine (DE) and 3 display IO ports configurable to eDP, DP or HDMI. In mobile SKUs, the peripheral control hub (PCH) resides in the same package (MCP) as the CPU and communicates through an on-package IO (OPIO) bus. For desktop (DT), the PCH resides on the platform. Fig. 4.1.1 presents the SKL block diagram for the minimum configuration (2 cores, 24 EU GP, MCP). A key challenge was the need to add new capabilities, while reducing power, especially for some of the popular uses (media, casual gaming, speech recognition and advanced imaging).

Frequency dependent efficiency model of on-chip DC-DC buck converters

An analytic method to evaluate frequency dependent losses in on-chip DC-DC buck converters is presented in this paper. These converters feature high switching losses caused by the skin effect in the package inductors. The frequency dependent air-core inductor model is shown to be critical in determining the optimal switching frequency. A general RLC parameter extraction method is also described. Considering the skin effect results in a 15% reduction in overall DC-DC converter losses. The proposed approach focuses on decreasing ripple current related losses, which are dominant in the target operating condition. Consequently, to obtain optimal efficiency, the switching frequency increases as the load current decreases. An intuitive explanation for this surprising result is that switching losses rise linearly with frequency whereas ripple losses decrease as n1.5. A SPICE based circuit model of a DC-DC converter is applied to validate the proposed analytic method.

8.7 Dual-use low-drop-out regulator/power gate with linear and on-off conduction modes for microprocessor on-die supply voltages in 14nm

In recent generations of microprocessors, there has been an increase in the number and types of processors integrated on the same die. For example, in [1] several IA (Intel architecture) cores have been integrated on-chip with a graphics processor. Multi-core trends are expected to increase in future generations with different cores and units requiring varying supply voltages. As platform footprints are also required to decrease, this causes a unique challenge for voltage regulation. In [2], an on-die switching fully integrated voltage regulator (FIVR) was demonstrated, which presents a very good solution in many cases. However, the FIVR requires inductors, which may not always be available. In addition, it may be desirable to sub-divide some of the FIVR domains using power gates and/or linear voltage regulators, such as low-drop-out regulators (LDO). LDOs can be used to enable different units of the chip to operate at their optimal voltage levels, which could save power. For example, different types of cores often have significantly different minimum-Vcc levels in low-power mode. In addition, a core or graphics unit could enter a high-performance mode, where the voltage is ramped up to enable performance, while other cores are in sleep or low-power modes.

Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On–Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm

A dual-mode digital power gate (PG) and linear low-drop-out regulator (LDO) has been demonstrated in 14 nm. A modified flipped source follower driver circuit is used to minimize dI/dt droops. The LDO has a novel compensation method which utilizes capacitance multiplication and can drive a 1-7 μF load without any external compensation elements. This LDO exhibits high-current drive capability (3 A) at low-dropout voltages (<; 60 mV) and high-current efficiency (> 99%), making it suitable to drive a microprocessor core.