Joseph Shor

Direct observation of porous SiC formed by anodization in HF

A process for forming porous SiC from single‐crystal SiC wafers has been demonstrated. Porous SiC can be fabricated by anodizing n‐type 6H‐SiC in HF under UV illumination. Transmission electron microscopy reveals pores of sizes 10–30 nm with interpore spacings ranging from ≊5 to 150 nm. This is the first reported direct observation of porous SiC formation.

Characterization of n-type beta -SiC as a piezoresistor

SiC is currently being investigated for device applications involving high temperatures. The properties of n-type beta -SiC relevant to piezoresistive devices, namely the gauge factor (GF) and temperature coefficient of resistivity (TCR), are characterized for several doping levels. The maximum gauge factor observed was -31.8 for unintentionally doped (10/sup 16/-10/sup 17//cm/sup 3/) material. This gauge factor decreases with temperature to approximately half its room-temperature value at 450 degrees C. Unintentionally doped SiC has a roughly constant TCR of 0.72%/ degrees C over the range 25-800 degrees C and exhibits full impurity ionization at room temperature. Degenerately doped gauges (N/sub d/=10/sup 20//cm/sup 3/) exhibited a lower gauge factor (-12.7), with a more constant temperature behavior and a lower TCR (0.04%/ degrees C). The mechanisms of the piezoresistive effect and TCR in n-SiC are discussed, as well as their application towards sensors. >

A fully integrated multi-CPU, GPU and memory controller 32nm processor

This paper describes the 32nm Sandy Bridge processor that integrates up to 4 high performance Intel Architecture (IA) cores, a power/performance optimized graphic processing unit (GPU) and memory and PCIe controllers in the same die. The Sandy Bridge architecture block diagram is shown in Fig. 15.1.1 and the floorplan of a four IA-core version is shown in Fig. 15.1.2. The Sandy Bridge IA core implements an improved branch prediction algorithm, a micro-operation (Uop) cache, a floating point Advanced Vector Extension (AVX), a second load port in the L1 cache and bigger register files in the out-of-order part of the machine; all these architecture improvements boost the IA core performance without increasing the thermal power dissipation envelope or the average power consumption (to preserve battery life in mobile systems). The CPUs and GPU share the same 8MB level-3 cache memory. The data flow is optimized by a high performance on die interconnect fabric (called “ring”) that connects between the CPUs, the GPU, the L3 cache and the system agent (SA) unit that houses a 1600MT/s, dual channel DDR3 memory controller, a 20-lane PCIe gen2 controller, a two parallel pipe display engine, the power management control unit and the testability logic. An on die EPROM is used for configurability and yield optimization.

Characterization of nanocrystallites in porous p-type 6H-SiC

We report the formation of porous p‐type 6H‐SiC. The existence of uniformly dispersed pores was confirmed by transmission electron microscopy, with interpore spacings in the range of 1–10 nm. The porous film as a whole is a single crystal. Luminescence peaks above the normal band gap of 6H‐SiC have been observed in the porous layer, but were not distinguished in the bulk SiC substrate. Quantum confinement is discussed as a possible mechanism for the luminescence effects.

Photoelectrochemical Etching of 6H-SiC

A new photoelectrochemical etching process is described for n-type 6H-SiC, while dark electrochemistry has been used to pattern p-type material. In this two-step etching process, the SiC is first anodized to form a deep porous layer, and this layer is subsequently removed by thermal oxidation followed by an HF dip. Etch rates as high as 4000 A/min for n-SiC and 2.2 μm/min for p-SiC have been obtained during the anodization, resulting in near mirror-like etched surfaces

Characterization of monolithic n-type 6H-SiC piezoresistive sensing elements

Monolithic, junction isolated piezoresistors have been fabricated in commercially available 6H-SiC. The gauge factor (GF) of these elements has been measured up to 250/spl deg/C in both longitudinal and transverse configurations. The maximum GF observed was -29.3, corresponding to the piezoresistive coefficient /spl pi//sub 11/. A beam transducer with a four-arm integral piezoresistor network was fabricated and tested in a force sensor configuration. The data indicate that, n-type 6H-SiC has the potential to be useful in high temperature electromechanical sensors to measure parameters such as pressure, force, strain and acceleration. >

Laser‐Assisted Photoelectrochemical Etching of n‐type Beta ‐ SiC

In this paper a nonthermal photoelectrochemical etching technique for β-SiC is reported. The measured etch rates of 1-100 μm/min in this process are much faster than other etching methods currently available for this material. UV radiation is necessary for efficient photogeneration of holes near the surface. These holes are transported in the presence of an external bias to the semiconductor/liquid interface, where dissolution occurs through the anodic oxidation of the SiC and the removal of the oxide by F - ions present in the electrolyte. The electrochemistry of -SiC and the etching process variables are discussed

Ratiometric BJT-based thermal sensor in 32nm and 22nm technologies

Thermal sensors are used in modern microprocessors to provide information for: 1) throttling at the maximum temperature of operation, and 2) fan regulation at temperatures down to 50°C. Todays microprocessors are thermally limited in many applications, so accurate temperature readings are essential in order to maximize performance. There are fairly large thermal gradients across the core, which vary for different instructions, so it is necessary to position thermal sensors near hot-spots. In addition, the locations of the hot-spots may not be predictable during the design phase. Thus it is necessary for hot-spot sensors to be small enough to be moved late in the design cycle or even after first Silicon.

Photoelectrochemical conductivity selective etch stops for SiC

Recent advances in SiC technology have demonstrated that the material is a potentially useful semiconductor for high temperature and high frequency applications. However, unlike silicon and GaAs, SiC is chemically inert, thus limiting the amount of etchants that can be effectively used to pattern devices. In fact, no patterning technique has been reported to date for SiC which shows high selectivity between p‐ and n‐type material. In this letter, we will show how an n‐type SiC epilayer can be patterned using photoelectrochemical etching, while a p‐type substrate underneath acts as an etch stop. This process is useful for the fabrication of electromechanical transducers, mesa structures, and bipolar and CMOS devices in SiC.

Miniaturized BJT-Based Thermal Sensor for Microprocessors in 32- and 22-nm Technologies

A thermal sensor is proposed for microprocessors, which compares the BJT voltage to a reference by converting both voltages to frequency and dividing the frequencies to result in a digital number. The sensor has an rms resolution of ±0.2C and an area of 0.02 mm2 at the 32-nm process node and 0.006 mm2 at 22 nm, including all digital processing circuitry. The conversion rate is between 2-20 kS/s, which enables it to capture fast transients on the CPU. It consumes 3.8/1.4 mW at 32/22 nm from an unregulated 1.4-V supply. The combination of speed, low power, and area make this sensor appropriate to measure hot-spots in microprocessors.