Michał Doligalski

UML state machine implementation in FPGA devices by means of dual model and Verilog

The paper presents the methodology of the logic controller development process based on the UML state machine diagram. The development process covers the logic synthesis and the implementation by means of the intermediate model based on Petri net formalism. The transformation between these two formal models is performed at the metamodels level according to the Model Driven Architecture (MDA). Semantics of the hierarchical configurable Petri net (HCfgPN) was adopted for the preemption and resumption mechanism. Operational subnet of HCfgPN model may be verified using formal methods.

Petri Net Dynamic Partial Reconfiguration in FPGA

The rigorous digital design of embedded Application Specific Logic Controllers starts from algorithm designed with concurrent hierarchical control interpreted Petri net and then implemented into FPGA. But, there could be required to have several contexts of work mode of such device. The classic design flows includes all contexts in one control algorithm together with switching handling. The design flow proposed in this paper uses feature of dynamic partial reconfiguration of new FPGA devices. There is proposed a way of design of a top level Petri net and subnets describing particular contexts and its connections. The rules of implementation are also formed.

Behavioral specification diversification for logic controllers implemented in FPGA devices

This paper deals with a new approach to logic controllers developing process. Classic development approach assumes the use of only one chosen model for the purpose of a logic controller specification. The proper choice of a model is a critical issue because drawbacks, advantages and specific characteristics of a controller will directly or indirectly affect each stage of a development process. A logic controller specification will have an influence on each stage of a development and, first of all, on an end product - namely, a logic controller and its quality. Diversification of the specification through the application of the Correlated State Machine and Hierarchical Configurable Petri Net (CSMHCPN) dual model brings out advantages of both component models eliminating, at the same time, their drawbacks. This paper presents an alternative approach to design logic controllers where at the specification stage two complementary models were used.

Behavioral specification of the logic controllers by means of the hierarchical configurable Petri nets

The paper introduces hierarchical configurable Petri nets theory, strictly based on the interpreted Petri nets. The application of a new method of specification simplifies the exceptions handling mechanism modeling in the Petri net notation. A simple manufacture process and its logic controller specification illustrate practical use of the new model.

Characterization of sprays for thermo-stabilized pneumatic nebulizer

The research presents the nebulizer spray chamber temperature controller responsible for controlling temperature of aerosol produced as a result of nebulizing process. The motivation to make an attempt to improve modern pneumatic devices was the shortage of this kind of apparatuses on the market allowing the production of thermos aerosol. A designed temperature controlling system for pneumatic nebulizers aims at increasing and stabilizing temperature of produced aerosols and increasing aerosol therapy safety. The system is intended for producing aerosol in the process of pneumatic nebulization with the temperature similar to that of the human body. Experiments that were carried out confirmed good performance of the device. It was proved that with the increase of temperature the amount of big droplets fall and the entire spectrum of the droplet diameter moves towards smaller droplet diameter values. Reduction of liquid viscosity related to the increase of temperature leads to the reduction of droplet diameter and, as a result, the reduction of the Sauter mean diameter value.

Exceptions Handling in Hierarchical Petri Net Based Specification for Logic Controllers

Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system[3]. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical Petri Net).

Design of Reconfigurable Logic Controllers

This bookpresents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the reconfigurable systems designing process or need ideas for improving the quality of the project, this book is a good choice.g process or need ideas for improving the quality of the project, this book is a good choice.

Role of UML Modelling in Discrete Controller Design

The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and statechart diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.

Unit testing-based approach for reconfigurable logic controllers verification

The paper presents unit testing-based approach to FPGA design in-circuit verification. Presented methodology is dedicated to modular reconfigurable logic controllers, but other ip-cores and systems can be verified as well. The speed and reproducibility of tests is key for rapid system prototyping, where the quality and reliability of the system is significance. Typically FPGA are programmed by means single (full) bitstream. Specific devices are able to be reconfigured partially. Usually the partial reconfiguration is a part of the design functionality. It enables the minimization of used resources or provides specific functionality like system adaptation. The paper presents the use of the partial reconfiguration as a toll for the designer. The unit testing approach well know form software engineering was adopted to modular logic controllers development. The simulation process results waveform files, the waveform can be used for synthesizable test bench generation.

Petri nets SM-cover based on heuristic coloring algorithm

In the paper, coloring heuristic algorithm of interpreted Petri nets is presented. Coloring is used to determine the State Machines (SM) subnets. The present algorithm reduces the Petri net in order to reduce the computational complexity and finds one of its possible State Machines cover. The proposed algorithm uses elements of interpretation of Petri nets. The obtained result may not be the best, but it is sufficient for use in rapid prototyping of logic controllers. Found SM-cover will be also used in the development of algorithms for decomposition, and modular synthesis and implementation of parallel logic controllers. Correctness developed heuristic algorithm was verified using Gentzen formal reasoning system.