Arkadiusz Bukowiec

Synthesis of Petri nets into FPGA with operation flexible memories

In this paper a new method of Petri net array-based synthesis is proposed. The method is based on the structured encoding of places by means of using minimal numbers of bits together with parallel decomposition of a digital system. State machine subnets, which are determined by colors are attached to places and transitions. Colored microoperations which are assigned to places are written into distributed and flexible memory. It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are used for generation of microoperations. Such an approach allows balanced usage of different kinds of resources available in modern FPGAs.

Theoretical Aspects of Petri Nets Decomposition Based on Invariants and Hypergraphs

Two methods of Petri nets decomposition into State Machine Components (SMCs) are shown in the paper. The first one bases on the well-known algorithm of place invariants (p-invariants) calculation. The second method applies hypergraph theory and computation of exact transversals. The aim of the paper is theoretical analysis of the effectiveness of presented methods. We show, that despite the high popularity, the achieved results generated by p-invariants are not always correct and spurious components ought to be eliminated. Furthermore, the effectiveness of the application of hypergraphs into Petri net decomposition is analysed.

Efficient logic controller design

Logic controller is a digital device used for automation of electromechanical processes, such as control of machinery on factory assembly line or lighting fixtures. This paper presents the method for designing a logic controller. We implement it using reprogrammable structure equipped with Embedded Memory Blocks, e.g. CPLD or FPGA. We find that specification of the controller with appropriate statechart diagram and further synthesis as equivalent Finite State Machine yields encouraging results: the number of programmable resources has been reduced approximately by 85%. Result of the research is illustrated with synthesis of practical controllers, where hardware resource consumption is presented. It shows the usefulness of the approach.1

Petri Net Dynamic Partial Reconfiguration in FPGA

The rigorous digital design of embedded Application Specific Logic Controllers starts from algorithm designed with concurrent hierarchical control interpreted Petri net and then implemented into FPGA. But, there could be required to have several contexts of work mode of such device. The classic design flows includes all contexts in one control algorithm together with switching handling. The design flow proposed in this paper uses feature of dynamic partial reconfiguration of new FPGA devices. There is proposed a way of design of a top level Petri net and subnets describing particular contexts and its connections. The rules of implementation are also formed.

An FPGA synthesis of the distributed control systems designed with Petri nets

The paper describes a new method for the synthesis of the application specific distributed control systems, constructed using the FPGA devices. The initial steps of the proposed control algorithm rely on the notion of a Petri net, which is an easy way to describe parallel processes. The subsequent steps of the algorithm consist in the decomposition of a given Petri net - with the use of a coloring algorithm - into a set of state machine type subnets. We think of each subnet as representing one parallel process. These subnets are then implemented independently in different FPGA devices. To ensure proper communication between all subnets, the entire control system uses a globally asynchronous locally synchronous (GALS) architecture with each subnet synchronized by the local clock signal. Global communication between components is buffer-based and uses additional signals, generated in a given subnet and distributed to the remaining ones.

Design of safety critical logic controller using devices integrated microprocessor with FPGA

In this paper, design of safety critical logic controller by means of programmable logic and microprocessor is described. The solution is based on duplicated Master-Slave architecture and results comparison from both pairs. The architecture was adapted to a FPGA device with embedded microprocessor -- in considered solution the Atmel FPSLIC was chosen. In design process tasks have been divided between hardware and software parts. The hardware part has been described in HDLs. The software for microprocessor has been written in its assembler or low-level C language. The process of verification that is based on simulation comparisons of solutions obtained in two different ways is also presented.

Design of Reconfigurable Logic Controllers

This bookpresents the original concepts and modern techniques for specification, synthesis, optimisation and implementation of parallel logical control devices. It deals with essential problems of reconfigurable control systems like dependability, modularity and portability. Reconfigurable systems require a wider variety of design and verification options than the application-specific integrated circuits. The book presents a comprehensive selection of possible design techniques. The diversity of the modelling approaches covers Petri nets, state machines and activity diagrams. The preferences of the presented optimization and synthesis methods are not limited to increasing of the efficiency of resource use. One of the biggest advantages of the presented methods is the platform independence, the FPGA devices and single board computers are some of the examples of possible platforms. These issues and problems are illustrated with practical cases of complete control systems. If you expect a new look at the reconfigurable systems designing process or need ideas for improving the quality of the project, this book is a good choice.g process or need ideas for improving the quality of the project, this book is a good choice.

Dual Simulation of Application Specific Logic Controllers Based on Petri Nets

The paper describes a new method of verification of the application specific logic controllers designed with use of Petri net. The method is oriented on behavioral simulation of post synthesis models. Two different method of logic synthesis are preformed for the same control algorithm described as Petri net. Then, obtained HDL models are used for dual simulation with result comparison. It allows to detect ambiguous construct in designed control algorithm.

Logic Synthesis for FPGAs of Interpreted Petri Net with Common Operation Memory

The method of synthesis of the logic circuit of interpreted Petri net is proposed in this paper. Proposed method is based on the minimal encoding of places. Places are encoded in subsets. Each subset is represented by one color of colored Petri net. Operations assigned to places are placed in memory. It leads to realization of logic circuit in two-level architecture, where the combinational circuit of first level is responsible for firing transitions and the second level memory is responsible for the generation of operations. Such approach allows balanced usage of different kinds of resources available in modern FPGAs.

Role of UML Modelling in Discrete Controller Design

The paper presents an application of UML technology in a discrete system development process. In the process at the analysis stage UML diagrams are fundamental tool. The outcome of this stage is a basis for formal models exploited at the design stage, where the design is symbolically verified and treated as a rule-based system. Two formal models of good graphical appeal are proposed: Petri nets and statechart diagrams. Both are heavily using Boolean expressions what makes that design can easily be implemented in modern programmable structures.