M. Mastrapasqua

Minimizing thermal resistance and collector-to-substrate capacitance in SiGe BiCMOS on SOI

We describe a low fabrication cost, high-performance implementation of SiGe BiCMOS on SOL The use of high-energy implant allows the simultaneous formation of the subcollector and an additional n-type region below the buried oxide. The combination of buried oxide layer and floating n-type region underneath results in a very low collector-to-substrate capacitance. We also show that this process option achieves a much lower thermal resistance than using SOI with deep trench isolation, both reducing cost and curbing self-heating effects.

Distributed effects in high power RF LDMOS transistors

This paper focuses on the effects of distributed RF transmission lines on performance aspects, such as, gain, output power, efficiency etc. in high power RF LDMOS amplifiers. The methodology to model and capture the distributed effects is discussed. Suitable alternatives to mitigate power loss due to distributive effects in large transistors are presented. Also, the contributions of the package to the overall device performance are addressed.

A drift-diffusion/Monte Carlo simulation methodology for Si/sub 1-x/Ge/sub x/ HBT design

An accurate and efficient simulation methodology for Si/sub 1-x/Ge/sub x/ HBTs is presented. A two-dimensional (2-D) drift-diffusion solver is employed for dc and ac characteristics, and one-dimensional (1-D) full-band Monte Carlo for transport in the base-collector high-electric-field region. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements and layout considerations. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. We discuss the calibration of the simulation on a 0.25 /spl mu/m process and use a 1-D regional analysis in the quasi-static approximation to identify the major source of delay. Results of the delay analysis were used to improve device performance for the 0.16 /spl mu/m technology node.

Monte Carlo simulation of impact ionization in SiGe HBTs

Measurements and Monte Carlo simulations of impact ionization in the base-collector region of SiGe HBTs are presented. A device with low germanium concentration (graded from 0 to 12%) is considered and no differences are found between the experimental multiplication factor in that device and the corresponding silicon control. Because impact ionization (II) occurs inside the bulk-Si collector, phonon and II scattering rates for bulk silicon can be used in the Monte Carlo simulation, avoiding the need to model the strained SiGe layers. Full-Band Monte Carlo simulations are shown to reproduce the multiplication factors measured in SiGe devices featuring different collector profiles.

High performance RF power LDMOSFET technology for 2.1GHz power amplifier applications

Silicon RF LDMOSFET technology is demonstrated with excellent RF performance. It achieves high power gain of 14.5dB with a high power of 130W at 2.1GHz. Its high efficiency and high linearity makes it highly desired for base station applications. 2mil substrate enables the best-in-class of thermal stability. Low HCI effect, integrated ESD and gold metal ensure high long-term reliability.

Thermal resistance in Si/sub 1-x/Ge/sub x/ HBTs on bulk-Si and SOI substrates

We present a characterization of self-heating in a 0.25 /spl mu/m SiGe BiCMOS technology on bulk and SOI substrates. Measurements are compared with analytical models and simulations. Thermal coupling between emitter fingers and effect of metallization are also analyzed.

COM2 enhanced graded base SiGe technology for high speed applications

The COM2 enhanced graded base SiGe modular BiCMOS technology has been developed. It is based on the COM2 digital CMOS process. The technology achieves peak f/sub t/=100 GHz, peak f/sub max/=101 GHz, peak /spl beta/=186 and BV/sub cex/=2.05 V. An f/sub t/-BV/sub cex/ product of 205 and good across wafer uniformity are demonstrated.

Device simulation for advanced Si/sub 1-x/Ge/sub x/ HBTs

Accurate simulations of advanced Si/sub 1-x/Ge/sub x/ heterojunction bipolar transistors involve a range of different problems, whose solution demands different numerical approaches. In our simulation methodology, the complexity of each numerical method matches that of the problem at hand. We employ a 2D drift-diffusion solver for dc and ac characteristics, 1D full-band Monte Carlo for transport in the base-collector high electric field region, and a 3D heat-transport solver for device self-heating. Extrinsic parasitics are introduced as lumped circuit elements whose values are obtained from measurements. This approach not only reduces the computational cost of the simulation, but it also helps to differentiate the relevance of the intrinsic and extrinsic device parameters. Such information can then be used for device optimization and for guidance in generating compact models.