Michel Renovell

Testing the interconnect of RAM-based FPGAs

Testing FPGAs before user programming can be an expensive procedure. Applying their general test configuration and test pattern generation methodology, the authors devise an efficient test procedure for the interconnect structure and demonstrate its applicability to commercial FPGAs.

Test of RAM-based FPGA: methodology and application to the interconnect

This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

Electrical analysis and modeling of floating-gate fault

It is demonstrated that a floating gate transistor (FGT) is influenced by its topological environment. The equivalent gate-to-source voltage of the FGT depends on the initial charges trapped in the gate oxide, the surrounding potential of metal lines and the drain-to-source voltage of the FGT itself. An electrical study of the floating gate fault is presented. A theoretical model taking into account the influence of the transistors environment is proposed. Analytical expressions for the equivalent gate-to-source voltage are derived, and the FGTs electrical operation mode is analyzed. This model is validated by SPICE simulations and by actual device measurements. The problem of testing for FGTs is discussed. >

Scan Design and Secure Chip

Testing a secure system is often considered as a severebottleneck. While testability requires to an increase inboth observability and controllability, secure chips aredesigned with the reverse in mind, limiting access to chipcontent and on-chip controllability functions. As a result,using usual design for testability techniques whendesigning secure ICs may seriously decrease the level ofsecurity provided by the chip. This dilemma is even moresevere as secure applications need well-tested hardwareto ensure that the programmed operations are correctlyexecuted. In this paper, a security analysis of the scantechnique is performed. This analysis aims at pointing outthe security vulnerability induced by using such a DfTtechnique. A solution securing the scan is finally proposed.

The concept of resistance interval: a new parametric model for realistic resistive bridging fault

From circuit measurement, it has been demonstrated that actual bridging faults have an intrinsic resistance mainly in the range from 0 /spl Omega/ to 500 /spl Omega/. This paper first analyses the consequences of this resistance on the electrical and logic behavior of bridging faults. Second, it is demonstrated that the classical models such as the voting model which consider the resistance as negligible, do not accurately and realistically represent the behavior of the fault. Third, a new parametric bridging fault model is proposed allowing to realistically represent the faulty behavior according to the intrinsic resistance which is not known a priori. Finally, a parametric bridging fault simulation algorithm is described together with some redefinition of the classical concepts of fault detection and fault coverage.

Towards an ADC BIST scheme using the histogram test technique

This paper discusses the viability of a BIST implementation for the sinusoidal histogram technique classically used for ADC testing. An original approach based on (i) approximations to estimate the ADC parameters, (ii) decomposition of the global test in a code-after-code test procedure and (iii) piecewise approximation to compute the ideal histogram is developed. These three features allow a significant reduction of the required operative resources as well as the required memory resources dedicated to the storage of both experimental and reference data.

Implementation of a linear histogram BIST for ADCs

This paper validates a linear histogram BIST scheme for ADC testing. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

A low-cost adaptive ramp generator for analog BIST applications

This paper presents a high-quality and area-efficient ramp generator to be used for on-chip testing of analog and mixed-signal circuits. An original adaptive scheme is developed to palliate the inaccuracy of a basic ramp generator. As a result, the proposed adaptive ramp generator exhibits very good performances in terms of slope precision and ramp linearity while maintaining a low area overhead.

Scan design and secure chip [secure IC testing]

Testing a secure system is often considered as a severe bottleneck. While testability requires an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability (DfT) techniques when designing secure ICs may seriously decrease the level of security provided by the chip. This dilemma is even more severe as secure applications need well-tested hardware to ensure that the programmed operations are correctly executed. In this paper, a security analysis of the scan technique is performed. This analysis aims at pointing out the security vulnerability induced by using such a DfT technique. A solution securing the scan is finally proposed.

A high accuracy triangle-wave signal generator for on-chip ADC testing

A general BIST architecture for A-to-D converters involves the integration of both an analog test signal generator and a digital output response analyzer. This paper presents a structure for the internal generation of a linear signal used with the histogram-based test technique. The structure is based on two highly linear ramp generators together with a feedback control circuitry. Results show that the proposed structure preserves the linearity of the ramp generators while accuracy of the triangle-wave is provided by means of a calibration scheme.