Mariane Comte

A Simulator of Small-Delay Faults Caused by Resistive-Open Defects

We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.

A new methodology for adc test flow optimization

Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application considering the most adequate trade-off between test time and test efficiency.

A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

Testing mixed-signal circuits remains one of the most difficult challenges within the semiconductor industry. In this article, the authors present a novel DFT technique to test sets of ADCs and DACs embedded in a complex SiP. The technique provides fully digital testing on the converters to significantly reduce the cost of testing

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors

Testing of Analog-to-Digital Converters is classically composed of two successive and independent phases: the histogram-based test technique evaluating static specifications and the spectral analysis technique evaluating the dynamic performances. Consequently, the fundamental objective here is to investigate the feasibility of an alternative test flow involving exclusively spectral analysis to replace these two time consuming and expensive phases. The viability of this solution depends on the ability of spectral analysis to detect static specifications. In this context, this paper presents a new methodology based on a statistical approach to quantitatively evaluate the efficiency of detecting static errors from dynamic parameter measurements. This methodology has been implemented in an in-house automatic tool allowing one to process any ADC specifications. It is then possible to choose a priori the best test flow for a given application.

Efficiency evaluation of analog/RF alternate test

The conventional practice for testing analog or RF integrated circuits is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring them directly. In this paper, we perform efficiency evaluation of this strategy, and in particular we perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is evaluated in terms of model accuracy by using classical metrics such as average and maximal prediction errors, and in terms of prediction reliability by introducing a new metric called Failing Prediction Rate (FPR). Results are illustrated on two case studies for which we have experimental test data.

MIRID: Mixed-Mode IR-Drop Induced Delay Simulator

IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching events at the logic gates are forwarded to the electrical model, where induced currents and their impact on the neighboring PDN nodes are computed. From this information, values of voltages at the Vdd and ground terminals of logic gates are determined, which in turn are used to calculate accurate switching delays of the gates. MIRID supports a generic interface to electrical models, allowing for a seamless integration of arbitrary models of PDN and gate timing. We report experiments based on a simple PDN model that was introduced previously and incorporates a pre-characterized library. The simulation accuracy is validated by matching the results from MIRID and SPICE.

Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect

In this paper, we analyze the electrical behavior of logic gates in presence of defect for different technologies. The final objective is to compare the defect detectability in a traditional planar Bulk technology, the emerging FDSOI and FinFET technologies. We implemented similar design in each technology and compared the electrical behavior with the same resistive short defect.

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and embedded computation of the table for LUT-based correction of ADC, we propose a new implementation establishing what we consider the best trade-off between silicon area overhead and computing time. We compare our solution with the state of the art: (a) with VHDL-level simulation we compare time performance, and (b) with FPGA placer we estimate the final surface head-out.

Analyzing the memory effect of resistive open in CMOS random logic

This paper analyzes the electrical behaviour of resistive opens as a function of its unpredictable resistance. It is demonstrated that the electrical behaviour depends on the value of the open resistance. It is also shown that, due to the memory effect detection of the open by a given vector Ti depends on all the vectors that have been applied to the circuit before Ti. An electrical analysis of this memory effect is presented

On the Use of Redundancy to Reduce Prediction Error in Alternate Analog/RF Test

Specification testing, which involves the direct measurement of the circuit performance parameters is the conventional practice for testing analog/RF devices. While this approach is highly accurate, it often incurs extremely high testing costs. A promising approach is to adopt alternate test strategy, i.e. a strategy in which test results are derived from indirect low-cost measurements. The underlying idea is to learn during a training phase the mapping between indirect measurements and circuit performance parameters, and to use only indirect measurements to predict device specifications during production testing. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited, mainly because confidence in alternate test predictions is difficult to assess. In this paper, we propose a novel implementation with the objective to improve confidence in alternate test predictions. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions and remove these devices from the alternate test flow. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.