Michele Petracca

A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer

An integrated voltage regulator (IVR) is presented that uses custom fabricated thin-film magnetic power inductors. The inductors are fabricated on a silicon interposer and integrated with a multi-phase buck converter IC by 2.5D chip stacking. Several inductor design variations have been fabricated and tested. The best performance has been achieved with a set of eight coupled inductors that each occupies 0.245 mm2 and provides 12.5 nH with 270 mΩ DC. With early inductor prototypes, the IVR efficiency for a 1.8 V:1.0 V conversion ratio peaks at 71% with FEOL current density of 10.8 A/mm2 and inductor current density of 1.53 A/mm2. At maximum load current, 69% conversion efficiency and 1.8 V:1.2 V conversion ratio the FEOL current density reaches 22.6 A/mm2 and inductor current density reaches 3.21 A/mm2.

Design Exploration of Optical Interconnection Networks for Chip Multiprocessors

The network-on-chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on chip (SoC) and chip multiprocessors (CMP). In future high performance CMPs, however, the high bandwidth requirements will not be adequately provided by electronic NoCs without dissipating large amounts of power. Previously, we have made the case for the photonic NoC as a unique interconnect solution for delivering scalable bandwidth-per-watt performance that surpasses equivalent electronic NoCs. Building on this work, we study the adoption of photonic communication for CMPs and we present three main contributions: (1) we propose two nonblocking topologies for photonic NoC designs and we assess both qualitatively and quantitatively the pros and cons that they offer with respect to the original (blocking) topology, (2) we show how a photonic NoC is better suited for a CMP made of complex multi-threaded cores, and (3) we present the first simulation based assessment of the benefits of using a photonic NoC for a real application, i.e. computing a large FFT.

Virtual channels vs. multiple physical networks: a comparative analysis

Packet-switched networks-on-chip (NoC) have been proposed as an efficient communication infrastructure for multi-core architectures. Adding virtual channels to a NoC helps to avoid deadlock and optimize the bandwidth of the physical channels in exchange for a more complex design of the routers. Another, possibly alternative, approach is to build multiple parallel physical networks (multi-planes) with smaller channels and simpler router organizations. We present a comparative analysis of these two approaches based on analytical models and on a comprehensive set of experimental results including both synthesized hardware implementations and system-level simulations.

Nanophotonic Optical Interconnection Network Architecture for On-Chip and Off-Chip Communications

An architecture for an integrated low-power, high-bandwidth optical interconnection network based on microring resonator technology is presented. The layout of the non-blocking network is described and a simulation-based performance evaluation is conducted.

Compositional system-level design exploration with planning of high-level synthesis

The growing complexity of System-on-Chip (SoC) design calls for an increased usage of transaction-level modeling (TLM), high-level synthesis tools, and reuse of pre-designed components. In the framework of a compositional methodology for efficient SoC design exploration we present three main contributions: a concise library format for characterization and reuse of components specified in high-level languages like SystemC; an algorithm to prune alternative implementations of a component given the context of a specific SoC design; and an algorithm that explores compositionally the design space of the SoC and produces a detailed plan to run high-level synthesis on its components for the final implementation. The two algorithms are computationally efficient and enable an effective parallelization of the synthesis runs. Through a case study, we show how our methodology returns the essential properties of the design space at the system level by combining the information from the library of components and by identifying automatically those having the most critical impact on the overall design.

Photonic NoCs: System-Level Design Exploration

Network-on-chip is a key enabling technology to address the challenges of interconnecting the increasing number of cores in emerging chip multiprocessors. By leveraging recent advances in the CMOS integration of photonic devices and the unique properties of the optical medium, photonic NoCs offer a promising solution to meet the communication requirements of chip multiprocessors with minimal draw from their power budget.

Scalability of Optical Interconnects Based on Microring Resonators

This letter investigates the use of optical microring resonators as switching elements (SEs) in large optical interconnection fabrics. We introduce a simple physical-layer model to assess scalability in crossbar- and Benes-based architectures. We also propose a new dilated SE that improves scalability to build fabrics of several terabits per second of aggregate capacity.

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI

A four-phase integrated buck converter in 45 nm silicon-on-insulator (SOI) technology is presented. The controller uses unlatched pulse-width modulation (PWM) with nonlinear gain to provide both stable small-signal dynamics and fast response (~700 ps) to large input and output transients. This fast control approach reduces the required output capacitance by 5× in comparison to a conventional, latched PWM controller at a similar operating point. The converter switches package-integrated air-core inductors at 80 MHz and delivers 1 A/mm2 at 83% efficiency and 0.66 conversion ratio. A network-on-chip (NoC) serves as a realistic digital load along with a programmable current source capable of generating load current steps with slew rate of ~1 A/100 ps for characterization of the control scheme.

A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm 2

Energy consumption is a dominant constraint on the performance of modern microprocessors and systems-on-chip. Dynamic voltage and frequency scaling (DVFS) is a promising technique for performing “on-the-fly” energy-performance optimization in the presence of workload variability. Effective implementation of DVFS requires voltage regulators that can provide many independent power supplies and can transition power supply levels on nanosecond timescales, which is not possible with modern board-level voltage regulator modules (VRMs) [1]. Switched-inductor integrated voltage regulators (IVRs) can enable effective implementation of DVFS, eliminating the need for separate VRMs and reducing power distribution network (PDN) impedance requirements by performing dc-dc conversion close to the load while supporting high peak current densities [2–3]. The primary obstacle facing development of IVRs is integration of suitable power inductors. This work presents an early prototype switched-inductor IVR using 2.5D chip stacking for inductor integration.

Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance

Virtual channels (VC) and multiple physical (MP) networks are two alternative methods to provide better performance, support quality-of-service, and avoid protocol deadlocks in packet-switched network-on-chip design. Since contention can be dynamically resolved, VCs give lower zero-load packet latency than MPs; however, MPs can be built with simpler routers and narrower channels, which improves the target clock frequency, power dissipation, and area occupation. In this paper, we present a comprehensive comparative analysis of these two design approaches, including an analytical model, synthesis-based designs with both FPGAs and standard-cell libraries, and system-level simulations. The result of our analysis shows that one solution does not outperform the other in all the tested scenarios. Instead, each approach has its own specific strengths and weaknesses. Hence, we identify the scenarios where each method is best suited to achieve high performance, very low power dissipation, and increased design flexibility.