Michiharu Tabe

Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs

A theoretical description is given of the dependence of the threshold voltage, V/sub TH/, of SOI MOSFETs on a wide range to top silicon layer thickness, t/sub s/, using both classical and quantum-mechanical methods. The quantum-mechanical effects become remarkable below the critical thickness and raise V/sub TH/ with decreasing t/sub s/. The classical method cannot be applied in such a thin t/sub s/ region, since classically obtained V/sub TH/ decreases monotonously with decreasing t/sub s/ even below the critical thickness. As a result, the V/sub TH/ curve as a function of t/sub s/ can be divided into two regions with a boundary at a critical t/sub s/, and the classical method can be applied above that critical thickness.<<ETX>>

Etching of SiO2 Films by Si in Ultra-High Vacuum

SiO2 etching resulting from reaction with impinging Si or substrate Si was clearly observed in an ultra-high vacuum by using step measurement, Auger electron spectroscopy and/or ellipsometry. In etching by impinging Si, the etching rate decreases with the substrate temperature, and increases with the Si impinging rate. These results are explained by a model proposed here that involves Si adsorption on SiO2, and a subsequent chemical reaction. It was found that SiO2 films thinner than 2.5 nm are etched by the same reaction with substrate Si, whereas those thicker than 2.5 nm are not etched at all, since reaction products cannot diffuse through the SiO2 film to the vacuum. These phenomena can be used in Si molecular beam epitaxy.

UV ozone cleaning of silicon substrates in silicon molecular beam epitaxy

This letter reports UV ozone cleaning of Si substrates for obtaining defect‐free molecular beam epitaxial films by low‐temperature in vacuum preheating. By using UV ozone cleaning, the high temperatures above 1200 °C required for removing surface carbon in the conventional method can be significantly lowered to below 1000 °C, since the UV ozone cleaning functions to remove carbon.

Photoluminescence from a Silicon Quantum Well Formed on Separation by Implanted Oxygen Substrate

We have observed strong photoluminescence (PL) from a well-defined two-dimensional (2D) Si structure formed on a SIMOX (separation by implanted oxygen) wafer, where the thin ( <5 nm) single crystalline silicon film is sandwiched between SiO2 layers. The PL intensity has a sharp maximum at a Si thickness of about 2 nm, whereas the peak photon energy of the PL spectra (1.65 eV) is almost independent of the Si thickness. These results can be interpreted with a three-region model in which electron-hole pairs are excited in the Si well and luminescence occurs at the upper and lower Si/SiO2 interfaces. Furthermore, temperature dependence of PL intensity in the present 2D system is found to be different from previously reported dependence in 0D or 1D Si structures.

Time‐resolved measurement of single‐electron tunneling in a Si single‐electron transistor with satellite Si islands

A Si single‐electron transistor (SET) with satellite Si islands has been fabricated by pattern‐dependent oxidation of cross‐shaped Si wires on a separation by implanted oxygen (SIMOX) substrate. The oscillatory conductance‐versus‐gate voltage characteristics of the SET show hysteresis as a result of abrupt jumps in the conductance at high temperatures around 30 K. This phenomenon is attributed to the memory effect of a single electron that tunnels between the SET Si island and the satellite Si islands. Time‐resolved measurements have clarified that the conductance jump is a Poisson process, which is clear evidence of the single‐electron tunneling between the Si islands.

Solid‐phase lateral epitaxy of chemical‐vapor‐deposited amorphous silicon by furnace annealing

A single‐crystalline silicon‐on‐insulator structure has been fabricated with solid‐phase lateral epitaxy. Chemical‐vapor‐deposited amorphous silicon (CVD a‐Si) deposited on a SiO2 stripe is crystallized by furnace annealing. A new CVD technique (clean CVD) has met the conditions required for solid‐phase epitaxy; clean interface and reduction of impurities and microcrystallites in the a‐Si film. In the case of a 4‐μm‐wide SiO2 stripe parallel to the 〈100〉 direction, the entire deposited layer grows epitaxially by low‐temperature furnace annealing (550∼650 °C). In the case of a 10‐μm‐wide SiO2 stripe, the whole surface region also grows epitaxially, although the deep region partially becomes polycrystalline in areas distant from the open substrate surface. The grown‐layer crystallinity is improved by subsequent high‐temperature annealing.

A new silicon‐on‐insulator structure using a silicon molecular beam epitaxial growth on porous silicon

A new silicon‐on‐insulator (SOI) structure has been achieved by utilizing silicon molecular beam epitaxial (Si‐MBE) growth on porous silicon, silicon island patterning, and the subsequent laterally enhanced oxidation of the porous silicon. The surface of Si‐MBE film grown on porous silicon at 770 °C without high‐temperature preheating has a 7×7 superlattice structure when observed by a reflection high‐energy electron diffraction (RHEED). Patterned Si‐MBE film island, that is 7.0 μm wide and 0.35 μm thick, is successfully isolated by the laterally enhanced oxidation of porous silicon.

Counter‐oxidation of superficial Si in single‐crystalline Si on SiO2 structure

This work proposes an oxidation mechanism for single‐crystalline Si overlying a buried SiO2 layer (SOI wafer). Experimental results show that not only the surface oxide but also the buried oxide layer of the SOI wafer grows during the thermal oxidation process. The oxidation behavior is analyzed with a simple model including oxygen diffusion through the superficial single crystalline Si layer, which agrees well with the experimental data. Furthermore, oxygen penetration through the superficial Si layer is verified by oxidation experiments using isotope oxygen.

Amorphous‐Si/crystalline‐Si facet formation during Si solid‐phase epitaxy near Si/SiO2 boundary

Amorphous‐Si (a‐Si)/crystalline‐Si (c‐Si) interface facet formation was found during Si solid‐phase epitaxy (SPE) near the Si/SiO2 boundary. A (110) facet is formed during (010)b‐[100]SPE (SPE growth in the [100] direction and near the (010) boundary between a‐Si and SiO2). A (111) facet is formed during (011)b‐[100]SPE. The facet formation is explained with an atomistic model wherein an a‐Si atom must complete at least two undistorted bonds to attain SPE growth, and the boundary condition wherein an a‐Si atom cannot form undistorted bond to Si/SiO2 boundary.

Fabrication of a silicon quantum wire surrounded by silicon dioxide and its transport properties

A novel fabrication method for ultrafine silicon wires is presented. To achieve electron physical confinement with a high potential SiO2 barrier, the SIMOX (separation by implanted oxygen) technique, electron beam lithography, anisotropic chemical etching, and thermal oxidation are used. The size of the wires is controlled by the lithography, the thickness of the top silicon layer and the thermal oxidation for narrowing the patterned silicon wire. The steplike structure in the conductance versus gate voltage curve, which remains up to higher temperatures for a smaller wire, suggests that a strong one‐dimensional transport effect occurs in this silicon wire.