Seiji Horiguchi

Ultimately thin double-gate SOI MOSFETs

The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

Quantum-mechanical effects on the threshold voltage of ultrathin-SOI nMOSFETs

A theoretical description is given of the dependence of the threshold voltage, V/sub TH/, of SOI MOSFETs on a wide range to top silicon layer thickness, t/sub s/, using both classical and quantum-mechanical methods. The quantum-mechanical effects become remarkable below the critical thickness and raise V/sub TH/ with decreasing t/sub s/. The classical method cannot be applied in such a thin t/sub s/ region, since classically obtained V/sub TH/ decreases monotonously with decreasing t/sub s/ even below the critical thickness. As a result, the V/sub TH/ curve as a function of t/sub s/ can be divided into two regions with a boundary at a critical t/sub s/, and the classical method can be applied above that critical thickness.<<ETX>>

ELECTRONIC STRUCTURES AND PHONON-LIMITED ELECTRON MOBILITY OF DOUBLE-GATE SILICON-ON-INSULATOR SI INVERSION LAYERS

Electronic structures and the phonon-limited electron mobility of inversion layers have been studied at 300 K for the thin Si (100) layer of double-gate (DG) silicon-on-insulator (SOI) structures by using a one-dimensional self-consistent calculation and a relaxation time approximation. Both symmetric and asymmetric DG SOI systems have been investigated. The self-consistent calculation presents the electronic structures specific to DG SOI Si inversion layers and the range of the specific electronic structures as functions of Si layer thickness tSi and the vertical effective electric field Eeff. Outside this range, the mobility behavior as a function of Eeff is almost identical to that of bulk Si inversion layers. In this range, however, as tSi decreases, the phonon-limited electron mobility μph increases gradually to a maximum around tSi=10 nm, decreases for tSi=10–5 nm, rises rapidly to another maximum in the vicinity of tSi=3 nm and finally falls. The former gradual increase in the mobility μph results ...

Mechanism of Potential Profile Formation in Silicon Single-Electron Transistors Fabricated Using Pattern-Dependent Oxidation

The origin of the potential profile in silicon single-electron transistors (SETs) fabricated using pattern-dependent oxidation (PADOX) is investigated by making use of the geometric structure measured by atomic force microscope (AFM), the bandgap reduction due to compressive stress generated during PADOX obtained using the first-principles calculation, and the effective potential method. A probable mechanism for the formation of the potential profile responsible for SET operation is proposed. The width reduction in the silicon wire region in the SET produces a tunnel barrier, while the compressive stress lowers the bottom of the conduction band through the bandgap reduction and forms a potential well corresponding to an island in the tunnel barrier.

Evaluation of interface potential barrier heights between ultrathin silicon oxides and silicon

Interface potential barrier heights for ultrathin silicon oxides (15– 44 A) on silicon and effective electron masses in some of these oxides are evaluated. Evaluation is performed using a new technique of analyzing the charging characteristics of metal‐nitride‐oxide‐semiconductor capacitors. Oxides thicker than 36 A have the same potential barrier heights as those for thick oxides, assuming the effective electron mass of the oxides is the same. However, for oxides thinner than 31 A, the potential barrier heights decrease and the effective electron masses increase as the oxide thickness decreases. These results suggest that oxides at least thicker than 36 A can be applied to metal‐oxide‐semiconductor field‐effect transistors as gate oxides.

Fabrication of Si single-electron transistors with precise dimensions by electron-beam nanolithography

Determining the relationship between wire size and the electrical characteristics of a single-electron transistor (SET) can significantly shorten the development time required to make SETs practical devices. In this study, this relationship was examined by fabricating SETs with precise dimensions using electron-beam nanolithography. The high-resolution resist HSQ provided fine wire patterns with small linewidth fluctuations. Si nanowires were made by etching using HSQ patterns as a mask, and then oxidized to produce SETs. The electrical characteristics were measured to determine the wire size required for making operational SETs. First, it was found that more oxidation widens the range of wire widths for which clear Coulomb blockade oscillations are observed. This is probably because more oxidation produces more oxidation-induced stress, which deepens the potential well essential for SET operation. In addition, it was experimentally confirmed that the gate capacitance is proportional to the nanowire lengt...

Fabrication of one-dimensional nanowire structures utilizing crystallographic orientation in silicon and their conductance characteristics

We propose a process for fabricating one-dimensional Si nanowires with a point contact. The nanowire structure can be easily obtained through two steps: KOH etching of a {110} Si layer of a silicon on insulator substrate and sufficient oxidation of the Si patterns formed by etching. In the etching process, vertical sidewalls comprised of {111} planes are formed into a wire. In addition, other {111} planes, projecting obliquely along the vertical sidewalls, spontaneously appear in the etched substrate. This is due to the fact that the etching proceeds as {111} planes appear because the etch rate of the {111} plane is the lowest of all planes. The bottom-corner region of two inclined {111} planes becomes a point-contact structure by making the distance between two inclined planes appropriate. The oxidation process converts the two-dimensional wire into one-dimensional nanowire by the stress-dependent oxidation phenomena of the Si wire. Consequently, a Si nanowire with a point contact can be formed in the bo...

Interface‐trap generation modeling of Fowler–Nordheim tunnel injection into ultrathin gate oxide

Two mechanisms for interface‐trap generation during Fowler–Nordheim tunnel injection into gate oxide are confirmed by the results of experiments with changes in the interface‐trap density for positive and negative gate bias injections. One mechanism is independent of gate bias polarity during injection, the other mechanism is present only in negative gate bias injection. Agreements between the measured and calculated generation cross sections for both mechanisms indicate that: (i) The first mechanism is quantitatively explained using a broken‐bond model by taking account of electron heating due to an oxide field during passage through the oxide conduction band. (ii) The second mechanism is quantitatively explained using a heated electron impact model where electrons heated by the oxide field generate interface traps by directly breaking the interface weak bonds when electrons cross the interface between the SiO2 and the Si substrate.

Investigation of SOI MOSFETs with ultimate thickness

Abstract Ultra-thin SOI MOSFETs with 1–5nm thick SOI film, are experimentally and theoretically investigated. Single- and double-gate configurations are compared; the double-gate MOSFET exhibits a substantial increase in transconductance, presumably resulting from volume inversion. Most of the experimental data can be explained by combining classical models with self-consistent quantum calculations. The characteristics are well-behaved and reveal unique “ultra-thin” film properties: enhanced interface coupling and body-substrate coupling, degraded mobility, increased threshold voltage.

Energy Eigenvalues and Quantized Conductance Values of Electrons in Si Quantum Wires on \mb{100\mb} Plane

A method to obtain the eigenstates of electrons in Si wires with arbitrary cross-sectional shapes and wire directions on the {100} plane is presented within the effective mass approximation, taking into account the six anisotropic valleys near the X points in bulk Si. In general, six equivalent valleys in bulk Si change to three pairs of doubly degenerate valleys in wires, and each pair has a quantized conductance value of 4e2/h (e is elementary charge and h is the Planck constant). In -oriented wires, two of the three pairs become fourfold degenerate and the quantized conductance value of these states becomes 8e2/h. Calculated energy levels for quantized motion perpendicular to the wire direction in wires with rectangular, triangular and trapezoidal cross sections show that the order of the energy levels in different degenerated pairs of valleys depends strongly on both the cross-sectional shape and the wire direction. It is also shown that calculated conductance as a function of gate voltage agrees with an experimental result semiquantitatively.