Michitarou Yabuuchi

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures

Reliability issues, such as soft errors, process variations and Negative Bias Temperature Instability (NBTI), become dominant on Field Programmable Gate Arrays (FPGAs) fabricated in a nanometer process. We focus on aging degradation by NBTI, which causes threshold voltage shifts on PMOS transistors. We characterize delay degradation in the routing structures on FPGAs. The rising and falling delays vary due to NBTI and heavily depend on circuit configurations. In the independent routing switch, the delay fluctuation due to NBTI can be minimized by transistor sizing. The falling delay does not change after 10-years degradation. In the routing structures composed of the routing switches and wires, the delay fluctuation depends on the wire length and can be minimized to optimize the wire length. We also show that the signal flipping can reduce the delay degradation from 11.3% to 2.76% on the routing resources.

Circuit characteristic analysis considering NBTI and PBTI-induced delay degradation

Bias Temperature Instability (BTI) becomes one of the most important reliability issues for nanometer process devices. We focus on aging degradation by BTI because it is known as one of the dominant factor that determines life time of circuits. In this paper, we show circuit delay degradation characteristic of BTI using the circuit simulation. The delay increase 15% after 10 years stress.

Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations

We show NBTI delay degradation considering variations in a 65nm process. We evaluate these two models. The homogeneous degradation model (HDM) assumes that NBTI degradation is constant at any variation and the inhomogeneous degradation model (IDM) assume that it is larger at the fast condition. In the usual logic gates on ASICs, delay degradation becomes much smaller on IDM. Circuit design guardbands can be reduced to ⅓ from the conventional pessimistic evaluations. As for FPGAs, we evaluate routing paths including level restorers and tristate inverters. The delay time after NBTI degradation is almost constant because of the pull-up PMOS in the level restorer.

Correlation between BTI-induced degradations and process variations by measuring frequency of ROs

We analyze the correlation between BTI (Bias Temperature Instability)-induced degradations and process variations. BTI shows a strong effect on highly scaled LSIs in the same way as the process variations. It is necessary to predict the combinational effects. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure initial frequencies and the aging-degradations of ROs (ring oscillators) of 65-nm process test circuits. The initial frequencies of ROs follow gaussian distributions. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition of the variations has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon on the variations is smaller than the average.

Initial and Long-Term Frequency Degradation on Ring Oscillators from Plasma Induced Damage in 65 nm Bulk and Silicon On Thin BOX processes

Degradation of reliability caused by plasma induced damage (PID) has become a significant concern with miniaturizing a device size. In this paper, we measure frequencies of ring oscillators with an antenna structure on a single stage. In bulk, PID is relieved by connecting an antenna to a drain because electric charge flow to a substrate. The difference of initial frequencies is 0.79 % between structures which cause and relieve PID. A Silicon On Thin BOX (SOTB) which has a buried oxide of less than 10 nm also relieves PID. Initial frequencies are affected by PID but there is no effect of PID in a long-term degradation mainly caused by bias temperature instability (BTI).

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS

As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results.

Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations

In this paper we outline a transistor size optimization technique for logic circuits that takes into account BTI (Bias Temperature Instability) and process variations. We demonstrate the accuracy of our results with statistical analysis. Since variations have a large impact on the scaling process, dependable circuit designs should include a quantitative analysis if they are to become more reliable in the future. In this study we used an algorithm to prove that with our technique we efficiently lowered the timing margin of the logic path by 4.4% below the margin achieved by conventional techniques. We also observed that the lifetime of the optimized circuits extended without any area overhead.

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

The degradation of reliability caused by plasma-induced damage (PID) has become a significant concern with the miniaturization of device size. In particular, it is difficult to relieve PID in silicon-on-insulator (SOI) because it contains buried oxide (BOX) layers. In this work, we compare PID between a bulk and a silicon on thin BOX (SOTB), which has BOX layers of less than 10 nm. We measure frequencies of ring oscillators with an antenna structure on a single stage. In the bulk, PID is relieved by first connecting an antenna to a drain because electric charge flows to a substrate. The difference in initial frequency is 0.79% between structures, which cause and relieve PID. SOTB also relieves the same amount of PID. Initial frequencies are affected by PID, but there is no effect of PID on the long-term degradation mainly caused by bias temperature instability (BTI).