Jun Furuta

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

We propose a Bistable Cross-coupled Dual Modular Redundancy (BCDMR) Flip-Flop to enhance soft-error immunity. It is based on a BISER FF but its bistable cross-coupled structure enhances soft-error immunity without any area, delay and power overhead. We fabricated a 65nm LSI including 60,480bit shift registers with the BCDMR and BISER structures. Experimental results using α-particles reveals that the soft-error immunity of the BCDMR is enhanced by 150x at 160MHz clock frequency compared with the BISER.

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.

Measurement of neutron-induced SET pulse width using propagation-induced pulse shrinking

We propose a single event transient (SET) pulse width measurement circuit using propagation-induced pulse shrinking on a clock buffer chain. It achieves the resolution of less than 1ps since the target circuit of the buffer chain is directly connected to the pulse capture FFs. Experimental results using the spallation neutron beam accelerated test show SET pulse widths are exponentially-distributed and number of SETs longer than 350 ps are reduced to 9% by inserting tap-cells closely. The SET rate on the clock buffer is 23x smaller than SEU rate on FFs.

Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets

We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.

A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop

We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the low-power (ACFF) and the highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent to the transmission-gate FF at 10% data activity while paying 3 × area penalty. Experiments by α-particle and neutron irradiation reveal its highly-reliable operations with no error at 1.2 V and 1 GHz. We measured five different process corner chips by α irradiation. Soft error rates are almost equivalent in these corner chips.

Parasitic bipolar effects on soft errors to prevent simultaneous flips of redundant flip-flops

Parasitic bipolar effects are intentionally used to prevent a simultaneous flip of redundant FFs, which make them more fault-resilient to soft errors. Device simulations reveal that a simultaneous flip of redundant latches is suppressed by storing the opposite values instead of storing the same value due to its asymmetrical structure. The state of latches always becomes a specific value after a particle hit due to the bipolar effects. Spallation neutron irradiation proves that no MCU is observed in the D-FF arrays in which the stored values of latches are equivalent to the specific value. The redundant latch structure storing the opposite values is robust to the simultaneous flip.

Dependence of Cell Distance and Well-Contact Density on MCU Rates by Device Simulations and Neutron Experiments in a 65-nm Bulk Process

Technology scaling increases the role of charge sharing and bipolar effect with respect to multiple cell upset. We analyze the contributions of cell distance and well-contact density to suppress MCU by device-level simulations and neutron experiments. Device simulation results reveal that the ratio of MCU to SEU exponentially decreases by increasing the distance between redundant latches. MCU is suppressed when well contacts are placed between redundant latches. Experimental results also show that the ratio of MCU to SEU exponentially decreases by increasing the distance between cells. MCU is suppressed effectively by increasing the density of well contacts.

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles

We fabricated a 65nm LSI including flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. It consists of two FF arrays as follows. One is an array composed of redundant FFs to confirm radiation hardness of the proposed and conventional redundant FFs. The other is an array composed of conventional D-FFs to measure SEU (Single Event Upset) and MCU(Multiple Cell Upset) by the distance from tap cells.

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm

We measures and investigate the correlation between well potential and SEUs to effectively detect SEUs by well potential perturbation. Cell-based perturbation detectors are implemented adjacent to FFs constructed a shift register. They measures the locations of voltage levels over 0.6 or 0.8 V. The measurement results by neutron irradiation on a 65nm bulk CMOS shows that almost 90% of SEUs are generated without any well potential perturbation. We also shows that the well-potential elevation over 0.8 V activates bipolar actions on neighbourhood transistors which prevents SEUs.

A Radiation-Hardened Non-Redundant Flip-Flop, Stacked Leveling Critical Charge Flip-Flop in a 65 nm Thin BOX FD-SOI Process

We propose SLCCFF which is a radiation hardened non-redundant flip-flop for an SOI process. The SLCCFF has the stacked structure to prevent soft errors on SOI processes while maintaining smaller delay and power overhead than conventional stacked FFs. Energy delay product of SLCCFF is 86% of the stacked FF. We fabricate test chip in a 65 nm thin BOX FDSOI process and measured soft error rates of SLCCFF, stacked FF and standard DFF by neutron irradiation and α particles. Experimental results show that the SLCCFF is about 27x stronger than the standard DFF at 0.4 V power supply in the SOTB process. It is about 1080x stronger compared with the standard DFF in the bulk process.