Miguel A. Martins

Techniques for Dual-Band LNA Design using Cascode Switching and Inductor Magnetic Coupling

In the last years we have assisted to a great development of wireless receivers working in narrow frequency bands. Nowadays, this development goes towards more flexible wireless receivers which accommodate different wireless applications - wide-band and multi-band receivers. In this paper we study techniques suitable for the design of dual-band CMOS low noise amplifiers (LNA), based on cascode switching and inductor magnetic coupling. Two LNA topologies were evaluated and implemented in a 0.35mum CMOS process. A proof of concept, a prototype of a proposed dual-band CMOS LNA was designed to work simultaneously at 0.9 GHz and 1.8 GHz. It uses a voltage supply of 2.4 V consuming 4.8 mA

A single-to-differential LNA topology with robust output gain-phase balancing against balun imbalance

This paper presents a technique to enhance the output balancing precision of a low-noise amplifier (LNA) against balun imbalance. By utilizing two capacitive-cross-coupling common-gate amplifiers in cascode, wideband output balancing, high voltage gain and low noise figure (NF) can be concurrently achieved. A 2.4GHz LNA design example optimized in a 0.13µm CMOS process shows that the tolerable baluns gain and phase imbalances are up to 2dB and 10°, respectively. With just 3.6mW of power, the NF is 2.6dB at a voltage gain of 30dB.

Multi-band combined LNA and mixer

In this paper we investigate the performance of the multi-band low noise amplifier (LNA) based on the concept of using multiple cascode transistors for band selection; thus, avoiding switches in the signal path. We also show that this circuit can perform mixing of two signal bands with two different local oscillator frequencies, which provides great flexibility in the design of dual-band RF front-ends. The operation of both as LNA and as combined LNA/mixer is demonstrated by simulation.

Fully Integrated Energy Harvesting Circuit With −25-dBm Sensitivity Using Transformer Matching

This brief presents a circuit to harvest energy from radio-frequency electromagnetic waves. It has a front-end transformer that simultaneously matches the harvesting circuit to a standard 50-Ω antenna and provides voltage gain, reducing the “dead-zone” of an 18-stage rectifier. The circuit is designed and prototyped in a standard 130-nm CMOS process with an active area of 200 × 250 μm2. Experimental results show a sensitivity of -25 dBm (-22 dBm without transformer) at 1.3 GHz.

Combined LNA and mixer circuits for 2.4 GHz ISM band

We present a combined LNA-Mixer circuit with low area and low power, for the 2.4 GHz ISM band. The circuit has two versions: one has an output RC low-pass filter suitable for low IF frequencies; the other has an output LC band-pass filter suitable for medium IF frequencies. Circuits, with IF of 50 MHz and 400 MHz, were designed using UMC 0.13 µm CMOS technology and 1.2 V supply, and dissipate approximately 7.6 mW.

An ISM 2.4 GHz low-IF receiver frontend

This paper describes the implementation of an RF receiver frontend for the 2.4 GHz ISM band; it comprises an LNA, an IQ oscillator/mixer, and a low-pass filter. The proposed circuit is low cost and power efficient. To be low cost the circuit is inductorless and implemented in a standard nanoscale digital CMOS technology, with a state-of-the-art figure for area. To be power efficient all the circuits were chosen based on their power efficiency. A contribution in this paper is a new, more efficient, IQ oscillator/mixer block, where the current is reduced by 25% and reused for the two functions. A prototype of a low-IF receiver frontend is designed in UMC 130nm CMOS technology and simulated with a post-layout including pads netlist, and off chip elements as bonding wires and load models. The frontend active area is 0.051 mm2 (die area with pads is 0.395 mm2), and the power consumption is 16.3 mW from a 1.2 V supply for a frontend gain of 27 dB.

SC biquad filter with hybrid utilization of OpAmp and comparator-based circuit

This paper proposes a differential switched-capacitor (SC) biquad filter exploiting a hybrid structure. The 1st active core is an operational amplifier (OpAmp) whereas the 2nd is an improved comparator-based circuit (CBC). The advantages of this new structure are justified by the reductions of power and transistor sizes. Optimized in a 65-nm CMOS process, when compared with a typical dual-OpAmp design, the proposed filter saves 19% power and 18% transistor area. The filter clocked at 40 MHz achieves 61.7-dB IM2 and 62.5-dB IM3 while drawing 2.23 mA from a 1.2-V supply. This hybrid SC biquad can gain further momentum for filters that request numerous biquads in cascade to attain higher selectivity.

A 0.02-to-6GHz SDR balun-LNA using a triple-stage inverter-based amplifier

This paper describes a software-defined-radio (SDR) balun low-noise amplifier (LNA) with no explicit bias circuit, inductor or ac-coupling network. It relies on a triple-stage inverter-based amplifier with resistive feedback to maximize the bandwidth and realize single-to-differential conversion. RC degeneration applied at the last gain stage enhances both linearity and output gain-phase balancing. Optimized in 65-nm CMOS the balun-LNA covers the 0.02-to-6-GHz band with S11>;-11 dB, voltage gain of 21.2-dB and noise figure below 3.2-dB. The in-band IIP2 (IIP3) is +36 to +51 dBm (-5.6 to -5.3 dBm). The power consumption is 7.9 mW at 1.2 V.

An Efficient RF power harvester for low input power with reduced dead-zone

Radio frequency energy harvesting circuits have to harvest energy from very weak sources demanding high sensitivity and high efficiency. In this paper, an efficient RF energy harvester for wireless sensor networks is presented. The circuit is based on a multi-stage rectifier that exploit threshold self-compensation together with transistor gate and bulk stimulus. The input is matched to 50Ω through a matching network that provides voltage boosting to the rectifiers input terminal. According to the desired performance, a 910MHz harvester with matched input comprising a 10-Stage rectifier has been designed in an 130-nm CMOS process. Considering a -20dB input power signal the circuit can supply a 1MΩ load with 1V/1μW output voltage and power with an PCE of 10%. The circuit exhibits a maximum PCE of 27% at -16dBm with 0.8V/6.4μW output voltage and power. The achieved results exceed the performance of previous work in terms of energy efficiency at input power lower than -15dBm.

A study on MOSFET rectifiers maximum output voltage for RF power harvesting circuits

Radio Frequency (RF) energy harvesting circuits have to harvest energy from very weak sources demanding high sensitivity and high efficiency. In this paper it is presented a study on rectifiers used in RF energy harvesting systems with MOSFET transistors operating in weak-inversion region, where both charge and discharge currents have the same order of magnitude. The study proves that the maximum output voltage of a MOSFET rectifier for very low input voltage is dependent in the first order to the relation between the signal amplitude and thermal voltage (VT). It is presented a method to calculate the maximum theoretical output voltage in two circuit topologies for input voltages of 10mV, 50mV and 100mV. The circuits are studied for 130nm, 90nm and 45nm CMOS technologies, proving the hypothesized theory that the maximum theoretical output voltage is not a function of the normal transistor parameters (i.e. Vt0, W/L) but instead, the relation between the input voltage amplitude and VT.